Hi Boris, On 09/24/2018 07:23 PM, Boris Brezillon wrote:
Hi Christophe, On Mon, 17 Sep 2018 17:47:39 +0200 <christophe.kerello@xxxxxx> wrote:+struct stm32_fmc2 { + struct nand_chip chip; + struct device *dev; + void __iomem *io_base; + void __iomem *data_base[FMC2_MAX_CE]; + void __iomem *cmd_base[FMC2_MAX_CE]; + void __iomem *addr_base[FMC2_MAX_CE]; + phys_addr_t io_phys_addr; + phys_addr_t data_phys_addr[FMC2_MAX_CE]; + struct clk *clk; + + struct dma_chan *dma_tx_ch; + struct dma_chan *dma_rx_ch; + struct dma_chan *dma_ecc_ch; + struct sg_table dma_data_sg; + struct sg_table dma_ecc_sg; + u8 *ecc_buf; + int dma_ecc_len; + + struct completion complete; + struct completion dma_data_complete; + struct completion dma_ecc_complete; + + struct stm32_fmc2_timings timings; + u8 cs_assigned; + int cs_sel; + int ncs; + int cs_used[FMC2_MAX_CE]; +};Can we have a clear separation between the NAND controller and NAND chip structures. I know you only support a single chip per-controller right now, but I prefer to have things clearly separated from the beginning.
Yes, I can create 2 structures: one for the controller (stm32_fmc2) and one for the NAND chip (stm32_fmc2_nand_chip).
Regards, Christophe Kerello.
Regards, Boris
