On 09/24/2018 03:42 PM, Thor Thayer wrote:
> On 09/24/2018 10:40 AM, Dinh Nguyen wrote:
>>
>>
>> On 09/19/2018 02:38 PM, thor.thayer@xxxxxxxxxxxxxxx wrote:
>>> From: Thor Thayer <thor.thayer@xxxxxxxxxxxxxxx>
>>>
>>> Add the SDRAM node to follow the Arria10 layout and
>>> bindings. The Arria10 SDRAM functions expect this
>>> node.
>>>
>>> Signed-off-by: Thor Thayer <thor.thayer@xxxxxxxxxxxxxxx>
>>> ---
>>> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 6 ++++++
>>> 1 file changed, 6 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
>>> b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
>>> index 78b4b06e8935..ee1d4b8ba631 100644
>>> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
>>> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
>>> @@ -467,6 +467,11 @@
>>> status = "disabled";
>>> };
>>> + sdr: sdr@ffc25000 {
>>
>> Should this be "sdr: sdr@f8011100" ?
>>
> Whoops. Yes, you are correct. I'll fix and resubmit. Thanks!
>
Feel free to add my ack when you resubmit.
Also, I noticed the same error in socfpga_arria10.dtsi, can you send a
patch to fix that too?
Thanks,
Dinh
