Hello Stephen,
On 8/24/2018 12:08 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-08 03:15:26)
On 8/8/2018 11:52 AM, Stephen Boyd wrote:
Binding describes hardware controllable by the OS. That's the reality.
Let's not add mandatory clock bindings for clocks that the OS can't do
anything about.
It seems that you believe clks should only be used to turn on/off and
control rates. That is not the whole truth. Sometimes clks are there
just to express the clk frequencies that are present in the design so
that drivers can figure out what to do.
Stephen,
As this clock is not configurable by linux clock drivers and we really
do not care the parent src(as mentioned by Saravana) to generate the
300MHz, would it be good to define a fixed rate clock so as to express
the HW connectivity & frequency?
As a hack that works great, but why do we need to workaround problems by
adding a fixed rate clk to DT for this PLL? The PLL is provided by GCC
node so it should be connected to the GCC node.
Please help with review the next patch series which would take the PLL
phandle from DT.
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