Hi Sakari, On Thu, Sep 13, 2018 at 01:19:12PM +0300, Sakari Ailus wrote: > On Thu, Sep 13, 2018 at 12:55:33PM +0300, Sakari Ailus wrote: > > Hi Jacopo, > > > > On Thu, Sep 13, 2018 at 11:46:14AM +0200, jacopo mondi wrote: > > > Hi Sakari, > > > > > > On Thu, Sep 13, 2018 at 12:29:35AM +0300, Sakari Ailus wrote: > > > > Initialise the V4L2 fwnode endpoints to zero in all drivers using > > > > v4l2_fwnode_endpoint_parse(). This prepares for setting default endpoint > > > > flags as well as the bus type. Setting bus type to zero will continue to > > > > guess the bus among the guessable set (parallel, Bt.656 and CSI-2 D-PHY). > > > > > > > > > > I've played around with this patch, trying to use defaults in the > > > renesas-ceu driver. > > > > > > This is the resulting patch, if you want I can send it as follow-up or > > > send it so that you can include it in your series if it's correct): > > > https://paste.debian.net/hidden/a7795d3e/ > > > > Looks nice; could you send it out to the list for review? > > > > The bus width default isn't specified in DT bindings; could you write a > > patch that defines it? > > Same for "pclk-sample". DT bindings do not document that; it should go to > the same patch. Actually it is 'wrong' to specify it in the default configuration in first place, as the interface does not support configuring the pixel clock edge on which to sample data. Same for data-shift, as the interface supports 8 or 16 bits only capture modes. I'll document bus_width restricting the accepted values to 8 and 16 and field-even-active as even if they're not actually implemented in the driver, they are configurable for the interface. Thanks j > > -- > Sakari Ailus > sakari.ailus@xxxxxxxxxxxxxxx
Attachment:
signature.asc
Description: PGP signature
