On Tue, Aug 21, 2018 at 08:58:30AM +0200, Sascha Hauer wrote: > On Mon, Aug 20, 2018 at 10:16:06AM +0300, Abel Vesa wrote: > > + > > + val |= (u32)value << divider->shift; > > + val |= (u32)value << PCG_DIV_SHIFT; > > + clk_writel(val, divider->reg); > > + > > + spin_unlock_irqrestore(divider->lock, flags); > > + > > + return 0; > > +} > > Have you tested this works? I thought those are two cascaded dividers > and you program both to the same value. Normally you would have to > calculate individual values for each divider which together give you the > desired output rate. > My bad. Haven't properly tested it since there is no actual driver that calls set_rate on any of those clocks at this point. Sorry about that. I'll send another version today, where I've implemented it as I should've done from the start and I've tested it by explicitly calling the set_rate and read the value with clk_get_rate to make sure it's fine. > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.pengutronix.de%2F&data=02%7C01%7Cabel.vesa%40nxp.com%7C722eb3cdb15849a9d19608d6073382e4%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636704315167487036&sdata=Q29pmTcLbqNPjotCFjZ%2BldD%2FBlbYpm6fN%2BzguHixwfA%3D&reserved=0 | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | --
