On 13 August 2018 07:55:34 BST, Taniya Das <tdas@xxxxxxxxxxxxxx> wrote: >Hello Craig, > >Could you please correct the authorship and also provide the reference >to code where this is picked from? Okay, Got code from here https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/drivers/clk/qcom/gcc-sdm660.c but changed it quite a bit for upstream, Should I change the commit author and add your signed off by and say I did cleanups on my signed off by. Also, hey, you wrote the original driver :) > >On 8/11/2018 1:51 AM, Craig Tatlor wrote: >> Add support for the global clock controller found on SDM660 >> based devices. This should allow most non-multimedia device >> drivers to probe and control their clocks. >> Based on CAF implementation. >> >> Signed-off-by: Craig Tatlor <ctatlor97@xxxxxxxxx> >> --- >> .../devicetree/bindings/clock/qcom,gcc.txt | 1 + >> drivers/clk/qcom/Kconfig | 9 + >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/gcc-sdm660.c | 2479 >+++++++++++++++++ >> include/dt-bindings/clock/qcom,gcc-sdm660.h | 159 ++ >> 5 files changed, 2649 insertions(+) >> create mode 100644 drivers/clk/qcom/gcc-sdm660.c >> create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt >b/Documentation/devicetree/bindings/clock/qcom,gcc.txt >> index 664ea1fd6c76..e498ad2e8db8 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt >> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt >> @@ -19,6 +19,7 @@ Required properties : >> "qcom,gcc-msm8996" >> "qcom,gcc-msm8998" >> "qcom,gcc-mdm9615" >> + "qcom,gcc-sdm660" >> "qcom,gcc-sdm845" >> >> - reg : shall contain base register location and length >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >> index 9c3480dcc38a..c4bda6d24c1f 100644 >> --- a/drivers/clk/qcom/Kconfig >> +++ b/drivers/clk/qcom/Kconfig >> @@ -226,6 +226,15 @@ config MSM_GCC_8998 >> Say Y if you want to use peripheral devices such as UART, SPI, >> i2c, USB, UFS, SD/eMMC, PCIe, etc. >> >> +config SDM_GCC_660 >> + tristate "SDM660 Global Clock Controller" >> + select QCOM_GDSC >> + depends on COMMON_CLK_QCOM >> + help >> + Support for the global clock controller on SDM660 devices. >> + Say Y if you want to use peripheral devices such as UART, SPI, >> + i2C, USB, UFS, SDDC, PCIe, etc. >> + >> config SDM_GCC_845 >> tristate "SDM845 Global Clock Controller" >> select QCOM_GDSC >> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile >> index 762c01137c2f..6e37d30d7c02 100644 >> --- a/drivers/clk/qcom/Makefile >> +++ b/drivers/clk/qcom/Makefile >> @@ -38,6 +38,7 @@ obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o >> obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o >> obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o >> obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o >> +obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o >> obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o >> obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o >> obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o >> diff --git a/drivers/clk/qcom/gcc-sdm660.c >b/drivers/clk/qcom/gcc-sdm660.c >> new file mode 100644 >> index 000000000000..bdb445aa4baa >> --- /dev/null >> +++ b/drivers/clk/qcom/gcc-sdm660.c >> @@ -0,0 +1,2479 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * Copyright (c) 2016-2017, The Linux Foundation. All rights >reserved. >> + * Copyright (c) 2018, Craig Tatlor. >> + */ >> + >> +#include <linux/kernel.h> >> +#include <linux/bitops.h> >> +#include <linux/err.h> >> +#include <linux/platform_device.h> >> +#include <linux/module.h> >> +#include <linux/of.h> >> +#include <linux/of_device.h> >> +#include <linux/clk-provider.h> >> +#include <linux/regmap.h> >> +#include <linux/reset-controller.h> >> + >> +#include <dt-bindings/clock/qcom,gcc-sdm660.h> >> + >> +#include "common.h" >> +#include "clk-regmap.h" >> +#include "clk-alpha-pll.h" >> +#include "clk-rcg.h" >> +#include "clk-branch.h" >> +#include "reset.h" >> +#include "gdsc.h" >> + >> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } >> + >> +enum { >> + P_XO, >> + P_SLEEP_CLK, >> + P_GPLL0, >> + P_GPLL1, >> + P_GPLL4, >> + P_GPLL0_EARLY_DIV, >> + P_GPLL1_EARLY_DIV, >> +}; >> + >> +static const struct parent_map >gcc_parent_map_xo_gpll0_gpll0_early_div[] = { >> + { P_XO, 0 }, >> + { P_GPLL0, 1 }, >> + { P_GPLL0_EARLY_DIV, 6 }, >> +}; >> + >> +static const char * const >gcc_parent_names_xo_gpll0_gpll0_early_div[] = { >> + "xo", >> + "gpll0", >> + "gpll0_early_div", >> +}; >> + >> +static const struct parent_map gcc_parent_map_xo_gpll0[] = { >> + { P_XO, 0 }, >> + { P_GPLL0, 1 }, >> +}; >> + >> +static const char * const gcc_parent_names_xo_gpll0[] = { >> + "xo", >> + "gpll0", >> +}; >> + >> +static const struct parent_map >gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = { >> + { P_XO, 0 }, >> + { P_GPLL0, 1 }, >> + { P_SLEEP_CLK, 5 }, >> + { P_GPLL0_EARLY_DIV, 6 }, >> +}; >> + >> +static const char * const >gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = { >> + "xo", >> + "gpll0", >> + "sleep_clk", >> + "gpll0_early_div", >> +}; >> + >> +static const struct parent_map gcc_parent_map_xo_sleep_clk[] = { >> + { P_XO, 0 }, >> + { P_SLEEP_CLK, 5 }, >> +}; >> + >> +static const char * const gcc_parent_names_xo_sleep_clk[] = { >> + "xo", >> + "sleep_clk", >> +}; >> + >> +static const struct parent_map gcc_parent_map_xo_gpll4[] = { >> + { P_XO, 0 }, >> + { P_GPLL4, 5 }, >> +}; >> + >> +static const char * const gcc_parent_names_xo_gpll4[] = { >> + "xo", >> + "gpll4", >> +}; >> + >> +static const struct parent_map >gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = >{ >> + { P_XO, 0 }, >> + { P_GPLL0, 1 }, >> + { P_GPLL0_EARLY_DIV, 3 }, >> + { P_GPLL1, 4 }, >> + { P_GPLL4, 5 }, >> + { P_GPLL1_EARLY_DIV, 6 }, >> +}; >> + >> +static const char * const >gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] >= { >> + "xo", >> + "gpll0", >> + "gpll0_early_div", >> + "gpll1", >> + "gpll4", >> + "gpll1_early_div", >> +}; >> + >> +static const struct parent_map >gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = { >> + { P_XO, 0 }, >> + { P_GPLL0, 1 }, >> + { P_GPLL4, 5 }, >> + { P_GPLL0_EARLY_DIV, 6 }, >> +}; >> + >> +static const char * const >gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = { >> + "xo", >> + "gpll0", >> + "gpll4", >> + "gpll0_early_div", >> +}; >> + >> +static const struct parent_map >gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = { >> + { P_XO, 0 }, >> + { P_GPLL0, 1 }, >> + { P_GPLL0_EARLY_DIV, 2 }, >> + { P_GPLL4, 5 }, >> +}; >> + >> +static const char * const >gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = { >> + "xo", >> + "gpll0", >> + "gpll0_early_div", >> + "gpll4", >> +}; >> + >> +static struct clk_fixed_factor xo = { >> + .mult = 1, >> + .div = 1, >> + .hw.init = &(struct clk_init_data){ >> + .name = "xo", >> + .parent_names = (const char *[]){ "xo_board" }, >> + .num_parents = 1, >> + .ops = &clk_fixed_factor_ops, >> + }, >> +}; >> + >> +static struct clk_alpha_pll gpll0_early = { >> + .offset = 0x0, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .clkr = { >> + .enable_reg = 0x52000, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll0_early", >> + .parent_names = (const char *[]){ "xo" }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_fixed_factor gpll0_early_div = { >> + .mult = 1, >> + .div = 2, >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll0_early_div", >> + .parent_names = (const char *[]){ "gpll0_early" }, >> + .num_parents = 1, >> + .ops = &clk_fixed_factor_ops, >> + }, >> +}; >> + >> +static struct clk_alpha_pll_postdiv gpll0 = { >> + .offset = 0x00000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gpll0", >> + .parent_names = (const char *[]){ "gpll0_early" }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_postdiv_ops, >> + }, >> +}; >> + >> +static struct clk_alpha_pll gpll1_early = { >> + .offset = 0x1000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .clkr = { >> + .enable_reg = 0x52000, >> + .enable_mask = BIT(1), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll1_early", >> + .parent_names = (const char *[]){ "xo" }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_fixed_factor gpll1_early_div = { >> + .mult = 1, >> + .div = 2, >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll1_early_div", >> + .parent_names = (const char *[]){ "gpll1_early" }, >> + .num_parents = 1, >> + .ops = &clk_fixed_factor_ops, >> + }, >> +}; >> + >> +static struct clk_alpha_pll_postdiv gpll1 = { >> + .offset = 0x1000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gpll1", >> + .parent_names = (const char *[]){ "gpll1_early" }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_postdiv_ops, >> + }, >> +}; >> + >> +static struct clk_alpha_pll gpll4_early = { >> + .offset = 0x77000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .clkr = { >> + .enable_reg = 0x52000, >> + .enable_mask = BIT(4), >> + .hw.init = &(struct clk_init_data){ >> + .name = "gpll4_early", >> + .parent_names = (const char *[]){ "xo" }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_alpha_pll_postdiv gpll4 = { >> + .offset = 0x77000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], >> + .clkr.hw.init = &(struct clk_init_data) >> + { >> + .name = "gpll4", >> + .parent_names = (const char *[]) { "gpll4_early" }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_postdiv_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = { >> + F(19200000, P_XO, 1, 0, 0), >> + F(50000000, P_GPLL0, 12, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { >> + .cmd_rcgr = 0x19020, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp1_qup1_i2c_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = { >> + F(960000, P_XO, 10, 1, 2), >> + F(4800000, P_XO, 4, 0, 0), >> + F(9600000, P_XO, 2, 0, 0), >> + F(15000000, P_GPLL0, 10, 1, 4), >> + F(19200000, P_XO, 1, 0, 0), >> + F(25000000, P_GPLL0, 12, 1, 2), >> + F(50000000, P_GPLL0, 12, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { >> + .cmd_rcgr = 0x1900c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp1_qup1_spi_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { >> + .cmd_rcgr = 0x1b020, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp1_qup2_i2c_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { >> + .cmd_rcgr = 0x1b00c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp1_qup2_spi_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { >> + .cmd_rcgr = 0x1d020, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp1_qup3_i2c_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { >> + .cmd_rcgr = 0x1d00c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp1_qup3_spi_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { >> + .cmd_rcgr = 0x1f020, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp1_qup4_i2c_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { >> + .cmd_rcgr = 0x1f00c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp1_qup4_spi_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = { >> + F(3686400, P_GPLL0, 1, 96, 15625), >> + F(7372800, P_GPLL0, 1, 192, 15625), >> + F(14745600, P_GPLL0, 1, 384, 15625), >> + F(16000000, P_GPLL0, 5, 2, 15), >> + F(19200000, P_XO, 1, 0, 0), >> + F(24000000, P_GPLL0, 5, 1, 5), >> + F(32000000, P_GPLL0, 1, 4, 75), >> + F(40000000, P_GPLL0, 15, 0, 0), >> + F(46400000, P_GPLL0, 1, 29, 375), >> + F(48000000, P_GPLL0, 12.5, 0, 0), >> + F(51200000, P_GPLL0, 1, 32, 375), >> + F(56000000, P_GPLL0, 1, 7, 75), >> + F(58982400, P_GPLL0, 1, 1536, 15625), >> + F(60000000, P_GPLL0, 10, 0, 0), >> + F(63157895, P_GPLL0, 9.5, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 blsp1_uart1_apps_clk_src = { >> + .cmd_rcgr = 0x1a00c, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp1_uart1_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp1_uart2_apps_clk_src = { >> + .cmd_rcgr = 0x1c00c, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp1_uart2_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { >> + .cmd_rcgr = 0x26020, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp2_qup1_i2c_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { >> + .cmd_rcgr = 0x2600c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp2_qup1_spi_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { >> + .cmd_rcgr = 0x28020, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp2_qup2_i2c_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { >> + .cmd_rcgr = 0x2800c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp2_qup2_spi_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { >> + .cmd_rcgr = 0x2a020, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp2_qup3_i2c_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { >> + .cmd_rcgr = 0x2a00c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp2_qup3_spi_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { >> + .cmd_rcgr = 0x2c020, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp2_qup4_i2c_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { >> + .cmd_rcgr = 0x2c00c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp2_qup4_spi_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp2_uart1_apps_clk_src = { >> + .cmd_rcgr = 0x2700c, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp2_uart1_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 blsp2_uart2_apps_clk_src = { >> + .cmd_rcgr = 0x2900c, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "blsp2_uart2_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gp1_clk_src[] = { >> + F(19200000, P_XO, 1, 0, 0), >> + F(100000000, P_GPLL0, 6, 0, 0), >> + F(200000000, P_GPLL0, 3, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gp1_clk_src = { >> + .cmd_rcgr = 0x64004, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div, >> + .freq_tbl = ftbl_gp1_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gp1_clk_src", >> + .parent_names = >gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, >> + .num_parents = 4, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gp2_clk_src = { >> + .cmd_rcgr = 0x65004, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div, >> + .freq_tbl = ftbl_gp1_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gp2_clk_src", >> + .parent_names = >gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, >> + .num_parents = 4, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gp3_clk_src = { >> + .cmd_rcgr = 0x66004, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div, >> + .freq_tbl = ftbl_gp1_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "gp3_clk_src", >> + .parent_names = >gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div, >> + .num_parents = 4, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = { >> + F(300000000, P_GPLL0, 2, 0, 0), >> + F(600000000, P_GPLL0, 1, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 hmss_gpll0_clk_src = { >> + .cmd_rcgr = 0x4805c, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_hmss_gpll0_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "hmss_gpll0_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = { >> + F(384000000, P_GPLL4, 4, 0, 0), >> + F(768000000, P_GPLL4, 2, 0, 0), >> + F(1536000000, P_GPLL4, 1, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 hmss_gpll4_clk_src = { >> + .cmd_rcgr = 0x48074, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll4, >> + .freq_tbl = ftbl_hmss_gpll4_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "hmss_gpll4_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll4, >> + .num_parents = 2, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = { >> + F(19200000, P_XO, 1, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 hmss_rbcpr_clk_src = { >> + .cmd_rcgr = 0x48044, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_hmss_rbcpr_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "hmss_rbcpr_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0, >> + .num_parents = 2, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_pdm2_clk_src[] = { >> + F(60000000, P_GPLL0, 10, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 pdm2_clk_src = { >> + .cmd_rcgr = 0x33010, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_pdm2_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "pdm2_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_qspi_ser_clk_src[] = { >> + F(19200000, P_XO, 1, 0, 0), >> + F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0), >> + F(160400000, P_GPLL1, 5, 0, 0), >> + F(267333333, P_GPLL1, 3, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 qspi_ser_clk_src = { >> + .cmd_rcgr = 0x4d00c, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = >gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, >> + .freq_tbl = ftbl_qspi_ser_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "qspi_ser_clk_src", >> + .parent_names = >gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div, >> + .num_parents = 6, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { >> + F(144000, P_XO, 16, 3, 25), >> + F(400000, P_XO, 12, 1, 4), >> + F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3), >> + F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2), >> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0), >> + F(100000000, P_GPLL0, 6, 0, 0), >> + F(192000000, P_GPLL4, 8, 0, 0), >> + F(384000000, P_GPLL4, 4, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 sdcc1_apps_clk_src = { >> + .cmd_rcgr = 0x1602c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div, >> + .freq_tbl = ftbl_sdcc1_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "sdcc1_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div, >> + .num_parents = 4, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = { >> + F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0), >> + F(150000000, P_GPLL0, 4, 0, 0), >> + F(200000000, P_GPLL0, 3, 0, 0), >> + F(300000000, P_GPLL0, 2, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 sdcc1_ice_core_clk_src = { >> + .cmd_rcgr = 0x16010, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_sdcc1_ice_core_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "sdcc1_ice_core_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = { >> + F(144000, P_XO, 16, 3, 25), >> + F(400000, P_XO, 12, 1, 4), >> + F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3), >> + F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2), >> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0), >> + F(100000000, P_GPLL0, 6, 0, 0), >> + F(192000000, P_GPLL4, 8, 0, 0), >> + F(200000000, P_GPLL0, 3, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 sdcc2_apps_clk_src = { >> + .cmd_rcgr = 0x14010, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4, >> + .freq_tbl = ftbl_sdcc2_apps_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "sdcc2_apps_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4, >> + .num_parents = 4, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_ufs_axi_clk_src[] = { >> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0), >> + F(100000000, P_GPLL0, 6, 0, 0), >> + F(150000000, P_GPLL0, 4, 0, 0), >> + F(200000000, P_GPLL0, 3, 0, 0), >> + F(240000000, P_GPLL0, 2.5, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 ufs_axi_clk_src = { >> + .cmd_rcgr = 0x75018, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_ufs_axi_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "ufs_axi_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = { >> + F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0), >> + F(150000000, P_GPLL0, 4, 0, 0), >> + F(300000000, P_GPLL0, 2, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 ufs_ice_core_clk_src = { >> + .cmd_rcgr = 0x76010, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_ufs_ice_core_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "ufs_ice_core_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 ufs_phy_aux_clk_src = { >> + .cmd_rcgr = 0x76044, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_sleep_clk, >> + .freq_tbl = ftbl_hmss_rbcpr_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "ufs_phy_aux_clk_src", >> + .parent_names = gcc_parent_names_xo_sleep_clk, >> + .num_parents = 2, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = { >> + F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0), >> + F(75000000, P_GPLL0, 8, 0, 0), >> + F(150000000, P_GPLL0, 4, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 ufs_unipro_core_clk_src = { >> + .cmd_rcgr = 0x76028, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_ufs_unipro_core_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "ufs_unipro_core_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_usb20_master_clk_src[] = { >> + F(19200000, P_XO, 1, 0, 0), >> + F(60000000, P_GPLL0, 10, 0, 0), >> + F(120000000, P_GPLL0, 5, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 usb20_master_clk_src = { >> + .cmd_rcgr = 0x2f010, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_usb20_master_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "usb20_master_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = { >> + F(19200000, P_XO, 1, 0, 0), >> + F(60000000, P_GPLL0, 10, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 usb20_mock_utmi_clk_src = { >> + .cmd_rcgr = 0x2f024, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_usb20_mock_utmi_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "usb20_mock_utmi_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_usb30_master_clk_src[] = { >> + F(19200000, P_XO, 1, 0, 0), >> + F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0), >> + F(120000000, P_GPLL0, 5, 0, 0), >> + F(133333333, P_GPLL0, 4.5, 0, 0), >> + F(150000000, P_GPLL0, 4, 0, 0), >> + F(200000000, P_GPLL0, 3, 0, 0), >> + F(240000000, P_GPLL0, 2.5, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 usb30_master_clk_src = { >> + .cmd_rcgr = 0xf014, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_usb30_master_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "usb30_master_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = { >> + F(19200000, P_XO, 1, 0, 0), >> + F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0), >> + F(60000000, P_GPLL0, 10, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 usb30_mock_utmi_clk_src = { >> + .cmd_rcgr = 0xf028, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div, >> + .freq_tbl = ftbl_usb30_mock_utmi_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "usb30_mock_utmi_clk_src", >> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div, >> + .num_parents = 3, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = { >> + F(1200000, P_XO, 16, 0, 0), >> + F(19200000, P_XO, 1, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 usb3_phy_aux_clk_src = { >> + .cmd_rcgr = 0x5000c, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_xo_sleep_clk, >> + .freq_tbl = ftbl_usb3_phy_aux_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "usb3_phy_aux_clk_src", >> + .parent_names = gcc_parent_names_xo_sleep_clk, >> + .num_parents = 2, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_branch gcc_aggre2_ufs_axi_clk = { >> + .ha -- Sent from my Android device with K-9 Mail. Please excuse my brevity.
