On Fri, Aug 10 2018 at 09:06 -0600, Stephen Boyd wrote:
Quoting Marc Zyngier (2018-08-10 00:45:12)
On Thu, 09 Aug 2018 18:30:53 +0100,
Stephen Boyd <swboyd@xxxxxxxxxxxx> wrote:
>
> Quoting Marc Zyngier (2018-08-07 23:26:32)
> >
> > Level interrupts should be taken care of without doing anything, by the
> > very nature of being a level signal.
>
> Right. I suspect we'll still need to configure the PDC to actually wake
> up on the level triggered signal though so PDC needs to be told to
> unmask the line.
Surely this can be done at suspend time with the PDC driver tracking
the interrupts that are configured as a wake-up source (although it
needs to track an interrupt that is logically connected to the TLMM,
which sucks).
The PDC also needs to be configured for wakeups from deep CPU idle
states where the GIC and TLMM are powered down. Lina, can you confirm
this?
Yes, it will need to be handled as part of CPU idle as well, when the
last CPU powers down.
Hooking system suspend in that case won't work. Is your hope that we can
avoid using hierarchical irqdomains here entirely?
Well, I wasn't trying to avoid hierarchical irqdomains, there were
restrictions in using it. Not all GPIO pins have parent in PDC and the
ones that have are all not from the same bank either.
-- Lina
