On Wed, Aug 08, 2018 at 08:29:50AM -0600, Rob Herring wrote:
> Version numbers on the individual patches would be nice...
We've never done these in the subsystems I'm involved with. Too
much clutter in the subject lines for information that is easily
deductable.
> > +Example:
> > +
> > + plic: interrupt-controller@c000000 {
> > + #address-cells = <0>;
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,plic0";
> > + interrupt-controller;
> > + interrupts-extended = <
> > + &cpu0-intc 11
> > + &cpu1-intc 11 &cpu1-intc 9
> > + &cpu2-intc 11 &cpu2-intc 9
> > + &cpu3-intc 11 &cpu3-intc 9
> > + &cpu4-intc 11 &cpu4-intc 9>;
>
> I'm confused why this is still here if you are dropping the cpu intc binding?
We need some parent that identifies the core (hart in RISC-V terminology).
The way the code now works is that it just walks up the parent chain
until it finds a CPU node, so it either accepts the legacy intc node
inbetween, or it accepts the cpu node directly as the intc node is pointless.
I guess for the documentation we should instead just point to the
"riscv" cpu nodes instead?
> I also noticed the cpu binding refers to "riscv,cpu-intc" as well.
> That needs to be fixed too if there's a change.
Only in the examples. I'd be fine with dropping them, but let's keep
that separate from the interrupt support.
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