On 2018-07-16 18:02, Rob Herring wrote:
+Optional properties:
+- port-number : Set Uart port number
+- clock-names : Should be "s_axi_aclk"
+- clocks : Input clock specifier. Refer to common clock bindings.
How do you calc baud rates if this is omitted?
The uartlite is fixed to some baud rate (actually divisor) in the fpga.
And btw. so are the number of data bits, stop bits and parity.
Maarten
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