Hi Venkat, Thank you for the patch! Yet something to improve: [auto build test ERROR on tegra/for-next] [also build test ERROR on v4.18-rc7 next-20180802] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Venkat-Reddy-Talla/soc-tegra-pmc-set-IO-pad-power-state-and-voltage-via-pinctrl-fw/20180803-043413 base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next config: arm64-defconfig (attached as .config) compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree GCC_VERSION=7.2.0 make.cross ARCH=arm64 Note: the linux-review/Venkat-Reddy-Talla/soc-tegra-pmc-set-IO-pad-power-state-and-voltage-via-pinctrl-fw/20180803-043413 HEAD ab02915682b2d61932e12e719422af7bc05b1eef builds fine. It only hurts bisectibility. All errors (new ones prefixed by >>): drivers/gpu//drm/tegra/sor.c: In function 'tegra_sor_edp_disable': >> drivers/gpu//drm/tegra/sor.c:1550:8: error: implicit declaration of function 'tegra_io_pad_power_disable'; did you mean 'tegra_pmc_io_pad_low_power_disable'? [-Werror=implicit-function-declaration] err = tegra_io_pad_power_disable(sor->pad); ^~~~~~~~~~~~~~~~~~~~~~~~~~ tegra_pmc_io_pad_low_power_disable drivers/gpu//drm/tegra/sor.c: In function 'tegra_sor_edp_enable': >> drivers/gpu//drm/tegra/sor.c:1710:8: error: implicit declaration of function 'tegra_io_pad_power_enable'; did you mean 'tegra_io_rail_power_on'? [-Werror=implicit-function-declaration] err = tegra_io_pad_power_enable(sor->pad); ^~~~~~~~~~~~~~~~~~~~~~~~~ tegra_io_rail_power_on cc1: some warnings being treated as errors vim +1550 drivers/gpu//drm/tegra/sor.c 6fad8f66d Thierry Reding 2014-11-28 1509 850bab448 Thierry Reding 2015-07-29 1510 static void tegra_sor_edp_disable(struct drm_encoder *encoder) 6fad8f66d Thierry Reding 2014-11-28 1511 { 850bab448 Thierry Reding 2015-07-29 1512 struct tegra_output *output = encoder_to_output(encoder); 850bab448 Thierry Reding 2015-07-29 1513 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 850bab448 Thierry Reding 2015-07-29 1514 struct tegra_sor *sor = to_sor(output); 850bab448 Thierry Reding 2015-07-29 1515 u32 value; 850bab448 Thierry Reding 2015-07-29 1516 int err; 850bab448 Thierry Reding 2015-07-29 1517 850bab448 Thierry Reding 2015-07-29 1518 if (output->panel) 850bab448 Thierry Reding 2015-07-29 1519 drm_panel_disable(output->panel); 850bab448 Thierry Reding 2015-07-29 1520 850bab448 Thierry Reding 2015-07-29 1521 err = tegra_sor_detach(sor); 850bab448 Thierry Reding 2015-07-29 1522 if (err < 0) 850bab448 Thierry Reding 2015-07-29 1523 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 850bab448 Thierry Reding 2015-07-29 1524 850bab448 Thierry Reding 2015-07-29 1525 tegra_sor_writel(sor, 0, SOR_STATE1); 850bab448 Thierry Reding 2015-07-29 1526 tegra_sor_update(sor); 850bab448 Thierry Reding 2015-07-29 1527 850bab448 Thierry Reding 2015-07-29 1528 /* 850bab448 Thierry Reding 2015-07-29 1529 * The following accesses registers of the display controller, so make 850bab448 Thierry Reding 2015-07-29 1530 * sure it's only executed when the output is attached to one. 850bab448 Thierry Reding 2015-07-29 1531 */ 850bab448 Thierry Reding 2015-07-29 1532 if (dc) { 850bab448 Thierry Reding 2015-07-29 1533 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); c57997bce Thierry Reding 2017-10-12 1534 value &= ~SOR_ENABLE(0); 850bab448 Thierry Reding 2015-07-29 1535 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 850bab448 Thierry Reding 2015-07-29 1536 850bab448 Thierry Reding 2015-07-29 1537 tegra_dc_commit(dc); 6fad8f66d Thierry Reding 2014-11-28 1538 } 6fad8f66d Thierry Reding 2014-11-28 1539 850bab448 Thierry Reding 2015-07-29 1540 err = tegra_sor_power_down(sor); 850bab448 Thierry Reding 2015-07-29 1541 if (err < 0) 850bab448 Thierry Reding 2015-07-29 1542 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 850bab448 Thierry Reding 2015-07-29 1543 9542c2376 Thierry Reding 2015-07-08 1544 if (sor->aux) { 9542c2376 Thierry Reding 2015-07-08 1545 err = drm_dp_aux_disable(sor->aux); 850bab448 Thierry Reding 2015-07-29 1546 if (err < 0) 850bab448 Thierry Reding 2015-07-29 1547 dev_err(sor->dev, "failed to disable DP: %d\n", err); 6fad8f66d Thierry Reding 2014-11-28 1548 } 6fad8f66d Thierry Reding 2014-11-28 1549 c57997bce Thierry Reding 2017-10-12 @1550 err = tegra_io_pad_power_disable(sor->pad); 850bab448 Thierry Reding 2015-07-29 1551 if (err < 0) c57997bce Thierry Reding 2017-10-12 1552 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 850bab448 Thierry Reding 2015-07-29 1553 850bab448 Thierry Reding 2015-07-29 1554 if (output->panel) 850bab448 Thierry Reding 2015-07-29 1555 drm_panel_unprepare(output->panel); 850bab448 Thierry Reding 2015-07-29 1556 aaff8bd2e Thierry Reding 2015-08-07 1557 pm_runtime_put(sor->dev); 6fad8f66d Thierry Reding 2014-11-28 1558 } 6fad8f66d Thierry Reding 2014-11-28 1559 459cc2c68 Thierry Reding 2015-07-30 1560 #if 0 459cc2c68 Thierry Reding 2015-07-30 1561 static int calc_h_ref_to_sync(const struct drm_display_mode *mode, 459cc2c68 Thierry Reding 2015-07-30 1562 unsigned int *value) 459cc2c68 Thierry Reding 2015-07-30 1563 { 459cc2c68 Thierry Reding 2015-07-30 1564 unsigned int hfp, hsw, hbp, a = 0, b; 459cc2c68 Thierry Reding 2015-07-30 1565 459cc2c68 Thierry Reding 2015-07-30 1566 hfp = mode->hsync_start - mode->hdisplay; 459cc2c68 Thierry Reding 2015-07-30 1567 hsw = mode->hsync_end - mode->hsync_start; 459cc2c68 Thierry Reding 2015-07-30 1568 hbp = mode->htotal - mode->hsync_end; 459cc2c68 Thierry Reding 2015-07-30 1569 459cc2c68 Thierry Reding 2015-07-30 1570 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp); 459cc2c68 Thierry Reding 2015-07-30 1571 459cc2c68 Thierry Reding 2015-07-30 1572 b = hfp - 1; 459cc2c68 Thierry Reding 2015-07-30 1573 459cc2c68 Thierry Reding 2015-07-30 1574 pr_info("a: %u, b: %u\n", a, b); 459cc2c68 Thierry Reding 2015-07-30 1575 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp); 459cc2c68 Thierry Reding 2015-07-30 1576 459cc2c68 Thierry Reding 2015-07-30 1577 if (a + hsw + hbp <= 11) { 459cc2c68 Thierry Reding 2015-07-30 1578 a = 1 + 11 - hsw - hbp; 459cc2c68 Thierry Reding 2015-07-30 1579 pr_info("a: %u\n", a); 459cc2c68 Thierry Reding 2015-07-30 1580 } 459cc2c68 Thierry Reding 2015-07-30 1581 459cc2c68 Thierry Reding 2015-07-30 1582 if (a > b) 459cc2c68 Thierry Reding 2015-07-30 1583 return -EINVAL; 459cc2c68 Thierry Reding 2015-07-30 1584 459cc2c68 Thierry Reding 2015-07-30 1585 if (hsw < 1) 459cc2c68 Thierry Reding 2015-07-30 1586 return -EINVAL; 459cc2c68 Thierry Reding 2015-07-30 1587 459cc2c68 Thierry Reding 2015-07-30 1588 if (mode->hdisplay < 16) 459cc2c68 Thierry Reding 2015-07-30 1589 return -EINVAL; 459cc2c68 Thierry Reding 2015-07-30 1590 459cc2c68 Thierry Reding 2015-07-30 1591 if (value) { 459cc2c68 Thierry Reding 2015-07-30 1592 if (b > a && a % 2) 459cc2c68 Thierry Reding 2015-07-30 1593 *value = a + 1; 459cc2c68 Thierry Reding 2015-07-30 1594 else 459cc2c68 Thierry Reding 2015-07-30 1595 *value = a; 459cc2c68 Thierry Reding 2015-07-30 1596 } 459cc2c68 Thierry Reding 2015-07-30 1597 459cc2c68 Thierry Reding 2015-07-30 1598 return 0; 459cc2c68 Thierry Reding 2015-07-30 1599 } 459cc2c68 Thierry Reding 2015-07-30 1600 #endif 459cc2c68 Thierry Reding 2015-07-30 1601 850bab448 Thierry Reding 2015-07-29 1602 static void tegra_sor_edp_enable(struct drm_encoder *encoder) 6fad8f66d Thierry Reding 2014-11-28 1603 { 850bab448 Thierry Reding 2015-07-29 1604 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 6fad8f66d Thierry Reding 2014-11-28 1605 struct tegra_output *output = encoder_to_output(encoder); 6fad8f66d Thierry Reding 2014-11-28 1606 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 6b6b60421 Thierry Reding 2013-11-15 1607 struct tegra_sor *sor = to_sor(output); 34fa183ba Thierry Reding 2014-06-05 1608 struct tegra_sor_config config; c31efa7a3 Thierry Reding 2015-09-08 1609 struct tegra_sor_state *state; 34fa183ba Thierry Reding 2014-06-05 1610 struct drm_dp_link link; 01b9bea0c Thierry Reding 2015-11-11 1611 u8 rate, lanes; 2bd1dd399 Thierry Reding 2015-08-03 1612 unsigned int i; 86f5c52dc Thierry Reding 2014-03-26 1613 int err = 0; 28fe20760 Thierry Reding 2015-01-26 1614 u32 value; 86f5c52dc Thierry Reding 2014-03-26 1615 c31efa7a3 Thierry Reding 2015-09-08 1616 state = to_sor_state(output->connector.state); 6b6b60421 Thierry Reding 2013-11-15 1617 aaff8bd2e Thierry Reding 2015-08-07 1618 pm_runtime_get_sync(sor->dev); 6b6b60421 Thierry Reding 2013-11-15 1619 6fad8f66d Thierry Reding 2014-11-28 1620 if (output->panel) 6fad8f66d Thierry Reding 2014-11-28 1621 drm_panel_prepare(output->panel); 6fad8f66d Thierry Reding 2014-11-28 1622 9542c2376 Thierry Reding 2015-07-08 1623 err = drm_dp_aux_enable(sor->aux); 6b6b60421 Thierry Reding 2013-11-15 1624 if (err < 0) 6b6b60421 Thierry Reding 2013-11-15 1625 dev_err(sor->dev, "failed to enable DP: %d\n", err); 34fa183ba Thierry Reding 2014-06-05 1626 9542c2376 Thierry Reding 2015-07-08 1627 err = drm_dp_link_probe(sor->aux, &link); 34fa183ba Thierry Reding 2014-06-05 1628 if (err < 0) { 01b9bea0c Thierry Reding 2015-11-11 1629 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 850bab448 Thierry Reding 2015-07-29 1630 return; 34fa183ba Thierry Reding 2014-06-05 1631 } 6b6b60421 Thierry Reding 2013-11-15 1632 25bb2cec8 Thierry Reding 2015-08-03 1633 /* switch to safe parent clock */ 25bb2cec8 Thierry Reding 2015-08-03 1634 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 6b6b60421 Thierry Reding 2013-11-15 1635 if (err < 0) 6b6b60421 Thierry Reding 2013-11-15 1636 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 6b6b60421 Thierry Reding 2013-11-15 1637 34fa183ba Thierry Reding 2014-06-05 1638 memset(&config, 0, sizeof(config)); c31efa7a3 Thierry Reding 2015-09-08 1639 config.bits_per_pixel = state->bpc * 3; 34fa183ba Thierry Reding 2014-06-05 1640 a198359e3 Thierry Reding 2015-07-21 1641 err = tegra_sor_compute_config(sor, mode, &config, &link); 34fa183ba Thierry Reding 2014-06-05 1642 if (err < 0) a198359e3 Thierry Reding 2015-07-21 1643 dev_err(sor->dev, "failed to compute configuration: %d\n", err); 34fa183ba Thierry Reding 2014-06-05 1644 6b6b60421 Thierry Reding 2013-11-15 1645 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 6b6b60421 Thierry Reding 2013-11-15 1646 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 6b6b60421 Thierry Reding 2013-11-15 1647 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 6b6b60421 Thierry Reding 2013-11-15 1648 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 6b6b60421 Thierry Reding 2013-11-15 1649 880cee0b7 Thierry Reding 2017-10-12 1650 value = tegra_sor_readl(sor, sor->soc->regs->pll2); a9a9e4fd7 Thierry Reding 2015-04-27 1651 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 880cee0b7 Thierry Reding 2017-10-12 1652 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 6b6b60421 Thierry Reding 2013-11-15 1653 usleep_range(20, 100); 6b6b60421 Thierry Reding 2013-11-15 1654 880cee0b7 Thierry Reding 2017-10-12 1655 value = tegra_sor_readl(sor, sor->soc->regs->pll3); a9a9e4fd7 Thierry Reding 2015-04-27 1656 value |= SOR_PLL3_PLL_VDD_MODE_3V3; 880cee0b7 Thierry Reding 2017-10-12 1657 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 6b6b60421 Thierry Reding 2013-11-15 1658 a9a9e4fd7 Thierry Reding 2015-04-27 1659 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | a9a9e4fd7 Thierry Reding 2015-04-27 1660 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; 880cee0b7 Thierry Reding 2017-10-12 1661 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 6b6b60421 Thierry Reding 2013-11-15 1662 880cee0b7 Thierry Reding 2017-10-12 1663 value = tegra_sor_readl(sor, sor->soc->regs->pll2); a9a9e4fd7 Thierry Reding 2015-04-27 1664 value |= SOR_PLL2_SEQ_PLLCAPPD; a9a9e4fd7 Thierry Reding 2015-04-27 1665 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; a9a9e4fd7 Thierry Reding 2015-04-27 1666 value |= SOR_PLL2_LVDS_ENABLE; 880cee0b7 Thierry Reding 2017-10-12 1667 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 6b6b60421 Thierry Reding 2013-11-15 1668 a9a9e4fd7 Thierry Reding 2015-04-27 1669 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; 880cee0b7 Thierry Reding 2017-10-12 1670 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 6b6b60421 Thierry Reding 2013-11-15 1671 6b6b60421 Thierry Reding 2013-11-15 1672 while (true) { 880cee0b7 Thierry Reding 2017-10-12 1673 value = tegra_sor_readl(sor, sor->soc->regs->pll2); a9a9e4fd7 Thierry Reding 2015-04-27 1674 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) 6b6b60421 Thierry Reding 2013-11-15 1675 break; 6b6b60421 Thierry Reding 2013-11-15 1676 6b6b60421 Thierry Reding 2013-11-15 1677 usleep_range(250, 1000); 6b6b60421 Thierry Reding 2013-11-15 1678 } 6b6b60421 Thierry Reding 2013-11-15 1679 880cee0b7 Thierry Reding 2017-10-12 1680 value = tegra_sor_readl(sor, sor->soc->regs->pll2); a9a9e4fd7 Thierry Reding 2015-04-27 1681 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; a9a9e4fd7 Thierry Reding 2015-04-27 1682 value &= ~SOR_PLL2_PORT_POWERDOWN; 880cee0b7 Thierry Reding 2017-10-12 1683 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 6b6b60421 Thierry Reding 2013-11-15 1684 6b6b60421 Thierry Reding 2013-11-15 1685 /* 6b6b60421 Thierry Reding 2013-11-15 1686 * power up 6b6b60421 Thierry Reding 2013-11-15 1687 */ 6b6b60421 Thierry Reding 2013-11-15 1688 6b6b60421 Thierry Reding 2013-11-15 1689 /* set safe link bandwidth (1.62 Gbps) */ 6b6b60421 Thierry Reding 2013-11-15 1690 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 6b6b60421 Thierry Reding 2013-11-15 1691 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 6b6b60421 Thierry Reding 2013-11-15 1692 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; 6b6b60421 Thierry Reding 2013-11-15 1693 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 6b6b60421 Thierry Reding 2013-11-15 1694 6b6b60421 Thierry Reding 2013-11-15 1695 /* step 1 */ 880cee0b7 Thierry Reding 2017-10-12 1696 value = tegra_sor_readl(sor, sor->soc->regs->pll2); a9a9e4fd7 Thierry Reding 2015-04-27 1697 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | a9a9e4fd7 Thierry Reding 2015-04-27 1698 SOR_PLL2_BANDGAP_POWERDOWN; 880cee0b7 Thierry Reding 2017-10-12 1699 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 6b6b60421 Thierry Reding 2013-11-15 1700 880cee0b7 Thierry Reding 2017-10-12 1701 value = tegra_sor_readl(sor, sor->soc->regs->pll0); a9a9e4fd7 Thierry Reding 2015-04-27 1702 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 880cee0b7 Thierry Reding 2017-10-12 1703 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 6b6b60421 Thierry Reding 2013-11-15 1704 880cee0b7 Thierry Reding 2017-10-12 1705 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 6b6b60421 Thierry Reding 2013-11-15 1706 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 880cee0b7 Thierry Reding 2017-10-12 1707 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 6b6b60421 Thierry Reding 2013-11-15 1708 6b6b60421 Thierry Reding 2013-11-15 1709 /* step 2 */ c57997bce Thierry Reding 2017-10-12 @1710 err = tegra_io_pad_power_enable(sor->pad); 850bab448 Thierry Reding 2015-07-29 1711 if (err < 0) c57997bce Thierry Reding 2017-10-12 1712 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); 6b6b60421 Thierry Reding 2013-11-15 1713 6b6b60421 Thierry Reding 2013-11-15 1714 usleep_range(5, 100); 6b6b60421 Thierry Reding 2013-11-15 1715 6b6b60421 Thierry Reding 2013-11-15 1716 /* step 3 */ 880cee0b7 Thierry Reding 2017-10-12 1717 value = tegra_sor_readl(sor, sor->soc->regs->pll2); a9a9e4fd7 Thierry Reding 2015-04-27 1718 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 880cee0b7 Thierry Reding 2017-10-12 1719 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 6b6b60421 Thierry Reding 2013-11-15 1720 6b6b60421 Thierry Reding 2013-11-15 1721 usleep_range(20, 100); 6b6b60421 Thierry Reding 2013-11-15 1722 6b6b60421 Thierry Reding 2013-11-15 1723 /* step 4 */ 880cee0b7 Thierry Reding 2017-10-12 1724 value = tegra_sor_readl(sor, sor->soc->regs->pll0); a9a9e4fd7 Thierry Reding 2015-04-27 1725 value &= ~SOR_PLL0_VCOPD; a9a9e4fd7 Thierry Reding 2015-04-27 1726 value &= ~SOR_PLL0_PWR; 880cee0b7 Thierry Reding 2017-10-12 1727 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 6b6b60421 Thierry Reding 2013-11-15 1728 880cee0b7 Thierry Reding 2017-10-12 1729 value = tegra_sor_readl(sor, sor->soc->regs->pll2); a9a9e4fd7 Thierry Reding 2015-04-27 1730 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 880cee0b7 Thierry Reding 2017-10-12 1731 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 6b6b60421 Thierry Reding 2013-11-15 1732 6b6b60421 Thierry Reding 2013-11-15 1733 usleep_range(200, 1000); 6b6b60421 Thierry Reding 2013-11-15 1734 6b6b60421 Thierry Reding 2013-11-15 1735 /* step 5 */ 880cee0b7 Thierry Reding 2017-10-12 1736 value = tegra_sor_readl(sor, sor->soc->regs->pll2); a9a9e4fd7 Thierry Reding 2015-04-27 1737 value &= ~SOR_PLL2_PORT_POWERDOWN; 880cee0b7 Thierry Reding 2017-10-12 1738 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 6b6b60421 Thierry Reding 2013-11-15 1739 30b494355 Thierry Reding 2015-08-03 1740 /* XXX not in TRM */ 30b494355 Thierry Reding 2015-08-03 1741 for (value = 0, i = 0; i < 5; i++) 30b494355 Thierry Reding 2015-08-03 1742 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | 30b494355 Thierry Reding 2015-08-03 1743 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 30b494355 Thierry Reding 2015-08-03 1744 30b494355 Thierry Reding 2015-08-03 1745 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 30b494355 Thierry Reding 2015-08-03 1746 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 30b494355 Thierry Reding 2015-08-03 1747 25bb2cec8 Thierry Reding 2015-08-03 1748 /* switch to DP parent clock */ 25bb2cec8 Thierry Reding 2015-08-03 1749 err = tegra_sor_set_parent_clock(sor, sor->clk_dp); 6b6b60421 Thierry Reding 2013-11-15 1750 if (err < 0) 25bb2cec8 Thierry Reding 2015-08-03 1751 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 6b6b60421 Thierry Reding 2013-11-15 1752 899451b78 Thierry Reding 2014-06-05 1753 /* power DP lanes */ 880cee0b7 Thierry Reding 2017-10-12 1754 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 899451b78 Thierry Reding 2014-06-05 1755 899451b78 Thierry Reding 2014-06-05 1756 if (link.num_lanes <= 2) 899451b78 Thierry Reding 2014-06-05 1757 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); 899451b78 Thierry Reding 2014-06-05 1758 else 899451b78 Thierry Reding 2014-06-05 1759 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; 899451b78 Thierry Reding 2014-06-05 1760 899451b78 Thierry Reding 2014-06-05 1761 if (link.num_lanes <= 1) 899451b78 Thierry Reding 2014-06-05 1762 value &= ~SOR_DP_PADCTL_PD_TXD_1; 899451b78 Thierry Reding 2014-06-05 1763 else 899451b78 Thierry Reding 2014-06-05 1764 value |= SOR_DP_PADCTL_PD_TXD_1; 899451b78 Thierry Reding 2014-06-05 1765 899451b78 Thierry Reding 2014-06-05 1766 if (link.num_lanes == 0) 899451b78 Thierry Reding 2014-06-05 1767 value &= ~SOR_DP_PADCTL_PD_TXD_0; 899451b78 Thierry Reding 2014-06-05 1768 else 899451b78 Thierry Reding 2014-06-05 1769 value |= SOR_DP_PADCTL_PD_TXD_0; 899451b78 Thierry Reding 2014-06-05 1770 880cee0b7 Thierry Reding 2017-10-12 1771 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 6b6b60421 Thierry Reding 2013-11-15 1772 a9a9e4fd7 Thierry Reding 2015-04-27 1773 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 6b6b60421 Thierry Reding 2013-11-15 1774 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 0c90a1846 Thierry Reding 2014-06-05 1775 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); a9a9e4fd7 Thierry Reding 2015-04-27 1776 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 6b6b60421 Thierry Reding 2013-11-15 1777 6b6b60421 Thierry Reding 2013-11-15 1778 /* start lane sequencer */ 6b6b60421 Thierry Reding 2013-11-15 1779 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 6b6b60421 Thierry Reding 2013-11-15 1780 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 6b6b60421 Thierry Reding 2013-11-15 1781 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 6b6b60421 Thierry Reding 2013-11-15 1782 6b6b60421 Thierry Reding 2013-11-15 1783 while (true) { 6b6b60421 Thierry Reding 2013-11-15 1784 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 6b6b60421 Thierry Reding 2013-11-15 1785 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 6b6b60421 Thierry Reding 2013-11-15 1786 break; 6b6b60421 Thierry Reding 2013-11-15 1787 6b6b60421 Thierry Reding 2013-11-15 1788 usleep_range(250, 1000); 6b6b60421 Thierry Reding 2013-11-15 1789 } 6b6b60421 Thierry Reding 2013-11-15 1790 a4263fed2 Thierry Reding 2014-06-05 1791 /* set link bandwidth */ 6b6b60421 Thierry Reding 2013-11-15 1792 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 6b6b60421 Thierry Reding 2013-11-15 1793 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; a4263fed2 Thierry Reding 2014-06-05 1794 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; 6b6b60421 Thierry Reding 2013-11-15 1795 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 6b6b60421 Thierry Reding 2013-11-15 1796 402f6bcd9 Thierry Reding 2015-07-21 1797 tegra_sor_apply_config(sor, &config); 402f6bcd9 Thierry Reding 2015-07-21 1798 402f6bcd9 Thierry Reding 2015-07-21 1799 /* enable link */ a9a9e4fd7 Thierry Reding 2015-04-27 1800 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 6b6b60421 Thierry Reding 2013-11-15 1801 value |= SOR_DP_LINKCTL_ENABLE; 6b6b60421 Thierry Reding 2013-11-15 1802 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; a9a9e4fd7 Thierry Reding 2015-04-27 1803 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 6b6b60421 Thierry Reding 2013-11-15 1804 6b6b60421 Thierry Reding 2013-11-15 1805 for (i = 0, value = 0; i < 4; i++) { 6b6b60421 Thierry Reding 2013-11-15 1806 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 6b6b60421 Thierry Reding 2013-11-15 1807 SOR_DP_TPG_SCRAMBLER_GALIOS | 6b6b60421 Thierry Reding 2013-11-15 1808 SOR_DP_TPG_PATTERN_NONE; 6b6b60421 Thierry Reding 2013-11-15 1809 value = (value << 8) | lane; 6b6b60421 Thierry Reding 2013-11-15 1810 } 6b6b60421 Thierry Reding 2013-11-15 1811 6b6b60421 Thierry Reding 2013-11-15 1812 tegra_sor_writel(sor, value, SOR_DP_TPG); 6b6b60421 Thierry Reding 2013-11-15 1813 6b6b60421 Thierry Reding 2013-11-15 1814 /* enable pad calibration logic */ 880cee0b7 Thierry Reding 2017-10-12 1815 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 6b6b60421 Thierry Reding 2013-11-15 1816 value |= SOR_DP_PADCTL_PAD_CAL_PD; 880cee0b7 Thierry Reding 2017-10-12 1817 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 6b6b60421 Thierry Reding 2013-11-15 1818 9542c2376 Thierry Reding 2015-07-08 1819 err = drm_dp_link_probe(sor->aux, &link); 850bab448 Thierry Reding 2015-07-29 1820 if (err < 0) 01b9bea0c Thierry Reding 2015-11-11 1821 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 6b6b60421 Thierry Reding 2013-11-15 1822 9542c2376 Thierry Reding 2015-07-08 1823 err = drm_dp_link_power_up(sor->aux, &link); 850bab448 Thierry Reding 2015-07-29 1824 if (err < 0) 01b9bea0c Thierry Reding 2015-11-11 1825 dev_err(sor->dev, "failed to power up eDP link: %d\n", err); 6b6b60421 Thierry Reding 2013-11-15 1826 9542c2376 Thierry Reding 2015-07-08 1827 err = drm_dp_link_configure(sor->aux, &link); 850bab448 Thierry Reding 2015-07-29 1828 if (err < 0) 01b9bea0c Thierry Reding 2015-11-11 1829 dev_err(sor->dev, "failed to configure eDP link: %d\n", err); 6b6b60421 Thierry Reding 2013-11-15 1830 6b6b60421 Thierry Reding 2013-11-15 1831 rate = drm_dp_link_rate_to_bw_code(link.rate); 6b6b60421 Thierry Reding 2013-11-15 1832 lanes = link.num_lanes; 6b6b60421 Thierry Reding 2013-11-15 1833 6b6b60421 Thierry Reding 2013-11-15 1834 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 6b6b60421 Thierry Reding 2013-11-15 1835 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 6b6b60421 Thierry Reding 2013-11-15 1836 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 6b6b60421 Thierry Reding 2013-11-15 1837 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 6b6b60421 Thierry Reding 2013-11-15 1838 a9a9e4fd7 Thierry Reding 2015-04-27 1839 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 6b6b60421 Thierry Reding 2013-11-15 1840 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 6b6b60421 Thierry Reding 2013-11-15 1841 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 6b6b60421 Thierry Reding 2013-11-15 1842 6b6b60421 Thierry Reding 2013-11-15 1843 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 6b6b60421 Thierry Reding 2013-11-15 1844 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 6b6b60421 Thierry Reding 2013-11-15 1845 a9a9e4fd7 Thierry Reding 2015-04-27 1846 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 6b6b60421 Thierry Reding 2013-11-15 1847 6b6b60421 Thierry Reding 2013-11-15 1848 /* disable training pattern generator */ 6b6b60421 Thierry Reding 2013-11-15 1849 6b6b60421 Thierry Reding 2013-11-15 1850 for (i = 0; i < link.num_lanes; i++) { 6b6b60421 Thierry Reding 2013-11-15 1851 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 6b6b60421 Thierry Reding 2013-11-15 1852 SOR_DP_TPG_SCRAMBLER_GALIOS | 6b6b60421 Thierry Reding 2013-11-15 1853 SOR_DP_TPG_PATTERN_NONE; 6b6b60421 Thierry Reding 2013-11-15 1854 value = (value << 8) | lane; 6b6b60421 Thierry Reding 2013-11-15 1855 } 6b6b60421 Thierry Reding 2013-11-15 1856 6b6b60421 Thierry Reding 2013-11-15 1857 tegra_sor_writel(sor, value, SOR_DP_TPG); 6b6b60421 Thierry Reding 2013-11-15 1858 6b6b60421 Thierry Reding 2013-11-15 1859 err = tegra_sor_dp_train_fast(sor, &link); 01b9bea0c Thierry Reding 2015-11-11 1860 if (err < 0) 01b9bea0c Thierry Reding 2015-11-11 1861 dev_err(sor->dev, "DP fast link training failed: %d\n", err); 6b6b60421 Thierry Reding 2013-11-15 1862 6b6b60421 Thierry Reding 2013-11-15 1863 dev_dbg(sor->dev, "fast link training succeeded\n"); 6b6b60421 Thierry Reding 2013-11-15 1864 6b6b60421 Thierry Reding 2013-11-15 1865 err = tegra_sor_power_up(sor, 250); 850bab448 Thierry Reding 2015-07-29 1866 if (err < 0) 6b6b60421 Thierry Reding 2013-11-15 1867 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 6b6b60421 Thierry Reding 2013-11-15 1868 6b6b60421 Thierry Reding 2013-11-15 1869 /* CSTM (LVDS, link A/B, upper) */ 143b1df23 Stéphane Marchesin 2014-05-22 1870 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 6b6b60421 Thierry Reding 2013-11-15 1871 SOR_CSTM_UPPER; 6b6b60421 Thierry Reding 2013-11-15 1872 tegra_sor_writel(sor, value, SOR_CSTM); 6b6b60421 Thierry Reding 2013-11-15 1873 2bd1dd399 Thierry Reding 2015-08-03 1874 /* use DP-A protocol */ 2bd1dd399 Thierry Reding 2015-08-03 1875 value = tegra_sor_readl(sor, SOR_STATE1); 2bd1dd399 Thierry Reding 2015-08-03 1876 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2bd1dd399 Thierry Reding 2015-08-03 1877 value |= SOR_STATE_ASY_PROTOCOL_DP_A; 2bd1dd399 Thierry Reding 2015-08-03 1878 tegra_sor_writel(sor, value, SOR_STATE1); 2bd1dd399 Thierry Reding 2015-08-03 1879 c31efa7a3 Thierry Reding 2015-09-08 1880 tegra_sor_mode_set(sor, mode, state); 2bd1dd399 Thierry Reding 2015-08-03 1881 6fad8f66d Thierry Reding 2014-11-28 1882 /* PWM setup */ 6fad8f66d Thierry Reding 2014-11-28 1883 err = tegra_sor_setup_pwm(sor, 250); 850bab448 Thierry Reding 2015-07-29 1884 if (err < 0) 6fad8f66d Thierry Reding 2014-11-28 1885 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 6b6b60421 Thierry Reding 2013-11-15 1886 666cb8733 Thierry Reding 2014-12-08 1887 tegra_sor_update(sor); 666cb8733 Thierry Reding 2014-12-08 1888 6fad8f66d Thierry Reding 2014-11-28 1889 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); c57997bce Thierry Reding 2017-10-12 1890 value |= SOR_ENABLE(0); 6fad8f66d Thierry Reding 2014-11-28 1891 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 6b6b60421 Thierry Reding 2013-11-15 1892 666cb8733 Thierry Reding 2014-12-08 1893 tegra_dc_commit(dc); 6b6b60421 Thierry Reding 2013-11-15 1894 6fad8f66d Thierry Reding 2014-11-28 1895 err = tegra_sor_attach(sor); 850bab448 Thierry Reding 2015-07-29 1896 if (err < 0) 6fad8f66d Thierry Reding 2014-11-28 1897 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 6b6b60421 Thierry Reding 2013-11-15 1898 6fad8f66d Thierry Reding 2014-11-28 1899 err = tegra_sor_wakeup(sor); 850bab448 Thierry Reding 2015-07-29 1900 if (err < 0) 6fad8f66d Thierry Reding 2014-11-28 1901 dev_err(sor->dev, "failed to enable DC: %d\n", err); 6b6b60421 Thierry Reding 2013-11-15 1902 6fad8f66d Thierry Reding 2014-11-28 1903 if (output->panel) 6fad8f66d Thierry Reding 2014-11-28 1904 drm_panel_enable(output->panel); a82752e19 Thierry Reding 2014-01-31 1905 } a82752e19 Thierry Reding 2014-01-31 1906 :::::: The code at line 1550 was first introduced by commit :::::: c57997bce423fb71334a1fefa524569e48a1718f drm/tegra: sor: Add Tegra186 support :::::: TO: Thierry Reding <treding@xxxxxxxxxx> :::::: CC: Thierry Reding <treding@xxxxxxxxxx> --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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