On Thu, 2 Aug 2018, Christoph Hellwig wrote: > On Thu, Aug 02, 2018 at 11:35:43AM +0200, Thomas Gleixner wrote: > > So that's the low level per cpu interrupt/exception distribution mechanism, > > i.e. a distinct per cpu 'vector' space with fixed functionality. It does > > not make sense to actually handle that as an irq chip. It has absolutely no > > relevance. The software interrupts are enabled when the CPU is started and > > the external ones as well as they are gated by the PLIC. > > > > The only thing which might need to access the enable register is the local > > timer interrupt. That really does not require an extra irq chip as the > > enable/disable is really just at cpu up/down time and the magic happens on > > the local CPU so no smp functional call hackery is required. > > > > The PLIC is the beast which wants a proper irqdomain/irqchip > > implementation. > > And that is exactly what I've done in the repost. Ok. > I need to polish the DT binding a little more and will repost later today. Lemme go through that reposted series quickly. Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
