On Tue, Jul 31, 2018 at 04:46:30PM -0600, Rob Herring wrote: > Perhaps this should be 'sifive,plic0' Excepet for the fact this the old name has already been in shipping hardware and release of qemu and other emulators it should. > Normally this would have an SoC specific compatible too. Sometimes we > can get away without, but it doesn't seem like the PLIC is very tightly > specified nor has common implementations. It is a giant f***cking mess to be honest. Adding a highlevel spec to the ISA but not a register layout is completely idotic, but if you look at the current riscv-sw list this decision is still defended by SiFive / the RISC-V foundation. The whole stale of the RISC-V platform Ecosystem is rather pathetic unfortunately, and people don't seem to be willing to learn from past good practice nor mistakes in ARM land. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
