Hello Again,
On Wed, Jun 27, 2018 at 11:40:00AM +0300, Matti Vaittinen wrote:
> Hello Stephen,
>
> On Mon, Jun 25, 2018 at 04:46:24PM -0700, Stephen Boyd wrote:
> > Quoting Matti Vaittinen (2018-06-13 06:03:38)
> > > On Tue, Jun 12, 2018 at 11:23:54AM +0300, Matti Vaittinen wrote:
> > > >
> > > > I see. This makes sense. I need to verify from HW colleagues whether
> > > > this chip has internal oscillator or not. I originally thought we have
> > > > on-chip oscillator - but as you say, we do have XIN pin in documentation.
> > > > So now I am not sure if the test board I have contains oscillator driving
> > > > the clk on PMIC - or if the PMIC has internal oscillator. I'll clarify this.
> > >
> > > It really turned out that the PMIC just acts as a clock buffer. So I do
> > > as you suggested and add lookup for parent clock to the driver. I
> > > planned to do it so that if no parent is found from DT - then we assume
> > > the 32.768KHz clock (as described in documentation). Eg, something along
> > > the lines:
> > >
> > > init.parent_names = of_clk_get_parent_name(pdev->dev.parent->of_node, 0);
> > > if (init.parent_names) {
> > > init.num_parents = 1;
> > > } else {
> > > /* If parent is not given from DT we assume the typical use-case with
> > > * 32.768 KHz oscillator for RTC (Maybe we could just error out here?)
> > > */
> > > c->rate = BD71837_CLK_RATE;
> > > bd71837_clk_ops.recalc_rate = &bd71837_clk_recalc_rate;
> > > }
> >
> > You can also add a clk directly in this driver in that case there isn't
> > one in DT with the rate and name of your choosing. Then the logic is the
> > same and we don't need a c->rate variable.
>
> So you mean that I should use clk_hw_register_fixed_rate and create new
> clk if parent is not found? Isn't this a bit of an overkill? Downside is
> that then we do need remove/cleanup functionality for deleting this
> parent clock - and I didn't find devm support for fixed clock. Furthermore
> I guess that since it is parent, it can't be removed before child is removed.
>
> Or did you mean something else but creating a fixed rate clock as parent
> here?
I would be grateful for any tips on how to proceed. Should I
1. Really create a fixed rate clock - and build cleanup sequence myself
2. Keep this simple and fail if no parent is found using of_clk_get_parent_name
Best regards
Matti Vaittinen
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