Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

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On Thu, Jul 26, 2018 at 5:21 PM, A.s. Dong <aisheng.dong@xxxxxxx> wrote:
> Hi Jassi,
>
>> -----Original Message-----
>> From: Jassi Brar [mailto:jassisinghbrar@xxxxxxxxx]
>> Sent: Thursday, July 26, 2018 5:50 PM
>> To: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
>> Cc: Shawn Guo <shawnguo@xxxxxxxxxx>; Fabio Estevam
>> <fabio.estevam@xxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>; Mark
>> Rutland <mark.rutland@xxxxxxx>; A.s. Dong <aisheng.dong@xxxxxxx>;
>> Vladimir Zapolskiy <vladimir_zapolskiy@xxxxxxxxxx>; , Sascha Hauer
>> <kernel@xxxxxxxxxxxxxx>; , linux-arm-kernel@xxxxxxxxxxxxxxxxxxx, linux-
>> mediatek@xxxxxxxxxxxxxxxxxxx, srv_heupstream <linux-arm-
>> kernel@xxxxxxxxxxxxxxxxxxx>; Devicetree List <devicetree@xxxxxxxxxxxxxxx>;
>> dl-linux-imx <linux-imx@xxxxxxx>
>> Subject: Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU
>> channel support
>>
>> On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
>> wrote:
>>
>> > Each MU has four pairs of rx/tx data register with four rx/tx
>> > interrupts which can also be used as a separate channel.
>> >
>> So the hardware actually supports 4 channels.
>>
>> > -- #mbox-cells:  Must be 0. Number of cells in a mailbox
>> > +- #mbox-cells:  Must be:
>> > +               0 - for single channel mode. i.MX8* SCU protocol specific.
>> > +               1 - for multichannel (generic) mode.
>> > +
>> No, please.
>> DT bindings should reflect the real hardware, and not the software mode we
>> want the driver to work in.
>> Please define mbox-cells=1  and have the i.MX8* platform always ask for
>> channel-0.
>
> The reality is that MU hardware does not define channels in reference manual.
> However, it does have four separate data tx/rx register which can be used
> as 'virtual' channels which is supported by this current driver.
>
> See below HW description from the reference manual:
> For messaging, the MU has four, 32-bit write-only transmit registers and four, 32-bit
> read-only receive registers on the Processor B and Processor A-sides. These registers are
> used for sending messages to each other.
>
> Passing short messages
> Transmit register(s) can be used to pass short messages
> from one to four words in length. For example, when a four-word message is desired,
> only one of the registers needs to have its corresponding interrupt enable bit set at the
> receiver side; the message’s first three words are written to the registers whose
> interrupt is masked, and the fourth word is written to the other register (which
> triggers an interrupt at the receiver side).
>
> The reference manual is at here: (Chapter 42 Messaging Unit (MU)
> https://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf
>
Thanks. That makes life much easier.

> And SCU firmware does use MU in above way specified by reference manual.
> Even from HW point of view, it's still one channel only mailbox.
> That's why we change the mbox-cells to 0 accordingly to avoid confusing
> the multi channels users supported in this driver.
>
> As per Sasha's request, we're going to support both protocol (SCU and generic M4)
> in one mailbox driver, that means we need deal with this two case property.
>
> If we use mbox-cells 1 case for SCU, then the using would be like:
> mboxes = <&mailbox 0> which is mixed with the normal multi channel
> users. And we also must state clearly in binding doc that for mbox-cells
>  1 case for SCU, the cell value must be 0 which is also confusing with
> Multi channel users.
>
> How do you suggest for such case?
>
Let me read the spec and try to see/shine the light :)

Cheers!
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