> -----Original Message----- > From: Li Yang [mailto:leoyang.li@xxxxxxx] > Sent: 2018年7月26日 5:19 > To: Wen He <wen.he_1@xxxxxxx> > Cc: Vinod <vkoul@xxxxxxxxxx>; dmaengine@xxxxxxxxxxxxxxx; Rob Herring > <robh+dt@xxxxxxxxxx>; open list:OPEN FIRMWARE AND FLATTENED DEVICE > TREE BINDINGS <devicetree@xxxxxxxxxxxxxxx>; Jiafei Pan > <jiafei.pan@xxxxxxx>; Jiaheng Fan <jiaheng.fan@xxxxxxx> > Subject: Re: [v7 4/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA > controller bindings > > On Wed, Jul 25, 2018 at 6:29 AM, Wen He <wen.he_1@xxxxxxx> wrote: > > Document the devicetree bindings for NXP Layerscape qDMA controller > > which could be found on NXP QorIQ Layerscape SoCs. > > > > Signed-off-by: Wen He <wen.he_1@xxxxxxx> > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > > --- > > Documentation/devicetree/bindings/dma/fsl-qdma.txt | 41 > ++++++++++++++++++++ > > 1 files changed, 41 insertions(+), 0 deletions(-) create mode 100644 > > Documentation/devicetree/bindings/dma/fsl-qdma.txt > > > > diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt > > b/Documentation/devicetree/bindings/dma/fsl-qdma.txt > > new file mode 100644 > > index 0000000..99b3d74 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt > > @@ -0,0 +1,41 @@ > > +NXP Layerscape SoC qDMA Controller > > +================================== > > + > > +This device follows the generic DMA bindings defined in dma/dma.txt. > > + > > +Required properties: > > + > > +- compatible: Must be one of > > + "fsl,ls1021a-qdma": for LS1021A Board > > + "fsl,ls1043a-qdma": for ls1043A Board > > + "fsl,ls1046a-qdma": for ls1046A Board > > Can you align on the case of "ls"? > OK > > +- reg: Should contain the register's base address and > length. > > +- interrupts: Should contain a reference to the interrupt used > by this > > + device. > > +- interrupt-names: Should contain interrupt names: > > + "qdma-error": the error interrupt > > + "qdma-queue": the queue interrupt > > +- fsl,queues: Should contain number of queues supported. > > This property name looks very general. Not sure if making it a little bit more > specific will be better such as "fsl,dma-queues". > Good idea, thank your comments. > > + > > +Optional properties: > > + > > +- dma-channels: Number of DMA channels supported > by the controller. > > +- big-endian: If present registers and hardware scatter/gather > descriptors > > + of the qDMA are implemented in big endian > mode, otherwise in little > > + mode. > > + > > +Examples: > > + > > + qdma: dma-controller@8390000 { > > + compatible = "fsl,ls1021a-qdma"; > > + reg = <0x0 0x8398000 0x0 0x2000 /* Controller > registers */ > > + 0x0 0x839a000 0x0 0x2000>; /* Block registers > */ > > + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 76 > IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "qdma-error", "qdma-queue"; > > + dma-channels = <8>; > > + queues = <2>; > > Not updated after the binding is updated. > What does means? Which one updated after the binding is update? Best Regards, Wen > > + big-endian; > > + }; > > + > > +DMA clients must use the format described in dma/dma.txt file. > > -- > > 1.7.1 > > > > -- > > To unsubscribe from this list: send the line "unsubscribe devicetree" > > in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo > > info at > > > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fvger > > .kernel.org%2Fmajordomo-info.html&data=02%7C01%7Cwen.he_1%4 > 0nxp.co > > > m%7Cf5c931a910a5410268fc08d5f2743fb2%7C686ea1d3bc2b4c6fa92cd99c > 5c30163 > > > 5%7C0%7C0%7C636681503456939918&sdata=zC57%2Bc9Ji2rjQY0KtNS > d8mlKgpp > > Jg2GqTeclwFy9Xjs%3D&reserved=0 ��.n��������+%������w��{.n����z�{��ܨ}���Ơz�j:+v�����w����ޙ��&�)ߡ�a����z�ޗ���ݢj��w�f
