On 17.07.2018 08:26, A.s. Dong wrote: >> -----Original Message----- >> From: Oleksij Rempel [mailto:o.rempel@xxxxxxxxxxxxxx] >> Sent: Tuesday, July 17, 2018 1:45 PM >> To: A.s. Dong <aisheng.dong@xxxxxxx>; Shawn Guo >> <shawnguo@xxxxxxxxxx>; Fabio Estevam <fabio.estevam@xxxxxxx>; Rob >> Herring <robh+dt@xxxxxxxxxx>; Mark Rutland <mark.rutland@xxxxxxx> >> Cc: devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; >> kernel@xxxxxxxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx> >> Subject: Re: [PATCH v3 1/3] dt-bindings: arm: fsl: add mu binding doc >> >> >> >> On 17.07.2018 07:00, A.s. Dong wrote: >>>> -----Original Message----- >>>> From: Oleksij Rempel [mailto:o.rempel@xxxxxxxxxxxxxx] >>>> Sent: Monday, July 16, 2018 7:42 PM >>>> To: Shawn Guo <shawnguo@xxxxxxxxxx>; Fabio Estevam >>>> <fabio.estevam@xxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>; Mark >>>> Rutland <mark.rutland@xxxxxxx>; A.s. Dong <aisheng.dong@xxxxxxx> >>>> Cc: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>; kernel@xxxxxxxxxxxxxx; >>>> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; >>>> dl-linux- imx <linux-imx@xxxxxxx> >>>> Subject: [PATCH v3 1/3] dt-bindings: arm: fsl: add mu binding doc >>>> >>>> The Messaging Unit module enables two processors within the SoC to >>>> communicate and coordinate by passing messages (e.g. data, status and >>>> control) through the MU interface. >>>> >>>> Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx> >>>> --- >>>> .../devicetree/bindings/mailbox/fsl,mu.txt | 32 >> +++++++++++++++++++ >>>> 1 file changed, 32 insertions(+) >>>> create mode 100644 >>>> Documentation/devicetree/bindings/mailbox/fsl,mu.txt >>>> >>>> diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt >>>> b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt >>>> new file mode 100644 >>>> index 000000000000..5d48dd75b98d >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt >>>> @@ -0,0 +1,32 @@ >>>> +NXP i.MX Messaging Unit (MU) >>>> +-------------------------------------------------------------------- >>>> + >>>> +Required properties: >>>> +------------------- >>>> +- compatible : should be "fsl,<chip>-mu", the supported chips >> include: >>>> + imx6sx - i.MX 6SoloX >>>> + imx7d - i.MX 7Dual >>>> + imx7s - i.MX 7Solo >>>> + imx7ulp - i.MX 7ULP >>>> + imx8qm - i.MX 8QM >>>> + imx8qxp - i.MX 8QXP >>>> +- reg : Should contain the registers location and length >>>> +- interrupts : Interrupt number. The interrupt specifier format >> depends >>>> + on the interrupt controller parent. >>>> +- #mbox-cells: Must be: >>>> + 0 - for single channel mode. i.MX8* SCU protocol specific. >>>> + 1 - for multichannel (generic) mode. >>>> + >>>> +Optional properties: >>>> +------------------- >>>> +- clocks : phandle to the input clock. >>>> +- fsl,mu-side-a : Should be set for side A MU. >>> >>> For this property, how about doing like: >>> fsl,mu-side: An Integer represents the MU side. >> >> All this SoCs have MUs with only two sides. Why do we need explicit >> annotation for both parts? >> >>> If missing this property, it's default to Side A >> >> So, why do we need optional integer, which is set by default as side A? >> This is why I made it bool. > > Yes, A bool probably is better. > >> >>> which is mostly used by A core. >> >> And you will need to explicit set side=B for SCU. Correct? > > SCU is using side A. AFAIK all SoC A core is using side A by default. > That's why I think it can be default one. User is free to specify both > In device tree. Does it make sense to you? Ok.
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