Hi Masahiro, Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx> wrote on Sat, 23 Jun 2018 01:06:33 +0900: > The ->setup_data_interface() hook needs to know the clock frequency. > In fact, this IP needs three clocks, but the current driver does not > represent it. Thus, it is hard to understand what is the correct > clock frequency. > (at least, clock property is not described in the DT-binding at all.) > > This series adds more clocks based on the IP datasheet, and document > it in the DT binding. > In the new binding, three clocks are required: core clock, bus interface > clock, ECC engine clock. > > 1/5 is a backport candidate to fix SOCFPGA. > > > Masahiro Yamada (5): > mtd: rawnand: denali_dt: set clk_x_rate to 200 MHz unconditionally > mtd: rawnand: denali_dt: use dev as a shorthand of &pdev->dev > dt-binding: mtd: denali_dt: document clock property > mtd: rawnand: denali_dt: add more clocks based on IP datasheet > mtd: rawnand: denali: optimize timing parameters for data interface Applied patches 2-5/5 to nand/next on top of v4-18.rc3 (to have the fix 1/5). Thanks, Miquèl -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
