On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec <jernej.skrabec@xxxxxxxx> wrote: > Some DW HDMI PHYs, like those found in A64 and R40 SoCs, can select > between two clock parents. > > Add code which reads second PLL from DT. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@xxxxxxxx> This patch by itself does not do anything. It should be merged with the next one. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
