Masahiro,
Am Freitag, 22. Juni 2018, 16:37:21 CEST schrieb Masahiro Yamada:
> Hi Richard,
>
>
> 2018-06-19 21:07 GMT+09:00 Richard Weinberger <richard@xxxxxx>:
> > The denali NAND flash controller needs at least two clocks to operate,
> > nand_clk and nand_x_clk.
> > Since 1bb88666775e ("mtd: nand: denali: handle timing parameters by
> > setup_data_interface()") nand_x_clk is used to derive timing settings.
> >
> > Signed-off-by: Richard Weinberger <richard@xxxxxx>
> > ---
> > Strictly speaking denali needs a ecc_clk too, but AFAIK such a clock
> > is not present on this SoC.
> > But my SoCFPGA knowledge is very limited.
> >
> > Thanks,
> > //richard
> > ---
> > arch/arm/boot/dts/socfpga.dtsi | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index 486d4e7433ed..562f7b375bbd 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -754,7 +754,8 @@
> > reg-names = "nand_data", "denali_reg";
> > interrupts = <0x0 0x90 0x4>;
> > dma-mask = <0xffffffff>;
> > - clocks = <&nand_clk>;
> > + clocks = <&nand_clk>, <&nand_x_clk>;
> > + clock-names = "nand", "nand_x";
>
>
> IMHO, this should be
>
> clocks = <&nand_clk>, <&nand_x_clk>, <&nand_x_clk>;
> clock-names = "nand", "nand_x", "ecc";
>
>
>
> A clock consumer (Denali in this case) should generally
> take the same number of clocks across SoCs.
>
> It is just some SoCs tie clocks together.
>
> It is the case for my UniPhier platform;
> "nand_x" and "ecc" are tied up because they are both 200MHz.
>
>
> SOCFPGA supports HW ECC correction, thus it surely needs ecc clock.
Good point!
Thanks,
//richard
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