On 18 June 2018 at 14:29, Benjamin Herrenschmidt
<benh@xxxxxxxxxxxxxxxxxxx> wrote:
> Add the device-tree binding definition for the AST2400
> and AST2500 coprocessor interrupt controller
>
> Signed-off-by: Benjamin Herrenschmidt <benh@xxxxxxxxxxxxxxxxxxx>
> ---
> .../devicetree/bindings/misc/aspeed,cvic.txt | 35 +++++++++++++++++++
> 1 file changed, 35 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/misc/aspeed,cvic.txt
>
> diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> new file mode 100644
> index 000000000000..2562e2991e4d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
Is there a reason you didn't put this in bindings/interrupt-controller?
Aside from that this looks good.
> @@ -0,0 +1,35 @@
> +* Aspeed AST2400 and AST2500 coprocessor interrupt controller
> +
> +This file describes the bindings for the interrupt controller present
> +in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
> +ColdFire coprocessor.
> +
> +It is not a normal interrupt controller and it would be rather
> +inconvenient to create an interrupt tree for it as it somewhat shares
> +some of the same sources as the main ARM interrupt controller but with
> +different numbers.
> +
> +The AST2500 supports a SW generated interrupt
> +
> +Required properties:
> +- reg: address and length of the register for the device.
> +- compatible: "aspeed,cvic" and one of:
> + "aspeed,ast2400-cvic"
> + or
> + "aspeed,ast2500-cvic"
> +
> +- valid-sources: One cell, bitmap of supported sources for the implementation
> +
> +Optional properties;
> +- copro-sw-interrupts: List of interrupt numbers that can be used as
> + SW interrupts from the ARM to the coprocessor.
> + (AST2500 only)
> +
> +Example:
> +
> + cvic: copro-interrupt-controller@1e6c2000 {
> + compatible = "aspeed,ast2500-cvic";
> + valid-sources = <0xffffffff>;
> + copro-sw-interrupts = <1>;
> + reg = <0x1e6c2000 0x80>;
> + };
> --
> 2.17.1
>
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