On 15/06/18 12:59, Amit Kucheria wrote: > On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das <tdas@xxxxxxxxxxxxxx> wrote: > [...] >> >> Yes I do understand the intent of mapping the whole register space, but as >> per the HW specs these 3 registers would be the only ones required for now. >> I do not think this hardware engine has any information on the power >> numbers. > > "For now" - I think this is exactly the point that Sudeep is trying to make. > > A future version of the HW engine, or more likely, a firmware > revision, will make more functionality available. Say, this needs > access to another register or two. This will require changing the DT > bindings. Instead, if you map the entire address space, you can just > add offsets to the new registers. > > So in this case, I think you should define the following addresses > (size 0x1400) for the two frequency domains > > 0x17d43000, 0x1400 (power cluster) > 0x17d45800, 0x1400 (perf cluster) > > And in the driver simply add offsets as follows: > > #define ENABLE_OFFSET 0x0 > #define LUT_OFFSET 0x110 > #define PERF_DESIRED_OFFSET 0x920 > > This will allow you add any new registers in the future w/o modifying > the DT binding and reduce qcom_cpu_resources_init() to a handful of > lines since you no longer need so many OF string matches, and > devm_ioremap()s. > Thanks Amit for such nice and detailed explanation. I was lazy to write in such details, but was hoping Taniya to understand the point. Anyways thanks again for doing this. -- Regards, Sudeep -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
