On Wed, Jun 13, 2018 at 9:28 PM, Rob Herring <robh@xxxxxxxxxx> wrote: >> "Some system-on-chips (SoCs) use the concept of GPIO banks. ... >> Usually each such bank is >> exposed in the device tree as an individual gpio-controller node. ..." > > This should be conditioned on being able to divide up the registers by > bank which seems like you can't. Or there's the case like the DW GPIO > block and the number of banks is configurable. If it is possible to create one device per bank I usually prefer that approach, as it also (often) makes it possible to use the generic GPIO library, i.e. the hardware abstraction start to share more with other GPIO controllers. >> If this is not a good approach, could you please me point me out to a >> device tree example where >> the correct approach is being used? > > I'm not sure offhand. There are lots of examples of single nodes I'm > sure. Which ones have banks I haven't a clue. IIRC, there were some > cases where the bank # was part of the GPIO cells, but I seem to > recall Linus prefers not having 3 cells. I don't like 3 cells, stuff is complicated enough as it is already. Better in that case to concatenate the offsets and instead of having an extra cell 0, 1 and offsets 0-31, 0-31 have two cells and offsets 0-63. My reasoning is that since it is represented by a single device we are indexing into that one device from 0-n. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
