Re: [PATCH 7/7] tty: serial: lantiq: Add CCF support

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On 6/13/2018 6:39 AM, Rob Herring wrote:
On Tue, Jun 12, 2018 at 01:40:34PM +0800, Songjun Wu wrote:
Previous implementation uses platform-dependent API to get the clock.
Those functions are not available for other SoC which uses the same IP.
The CCF (Common Clock Framework) have an abstraction based APIs
for clock.
Change to use CCF APIs to get clock and rate.
So that different SoCs can use the same driver.
Clocks and clock-names are updated in device tree binding.

Signed-off-by: Songjun Wu <songjun.wu@xxxxxxxxxxxxxxx>

---

  .../devicetree/bindings/serial/lantiq_asc.txt      |  15 +++
Please split bindings to separate patch.
Thanks.
It will be split to two separate patches, one for bindings, the other for code.
  drivers/tty/serial/Kconfig                         |   2 +-
  drivers/tty/serial/lantiq.c                        | 101 +++++++++++++++++----
  3 files changed, 98 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
index 3acbd309ab9d..608f0c87a4af 100644
--- a/Documentation/devicetree/bindings/serial/lantiq_asc.txt
+++ b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
@@ -6,6 +6,10 @@ Required properties:
  - interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
    depends on the interrupt-parent interrupt controller.
+Optional properties:
+- clocks: Should contain frequency clock and gate clock
+- clock-names: Should be "freq" and "asc"
+
  Example:
asc1: serial@e100c00 {
@@ -14,3 +18,14 @@ asc1: serial@e100c00 {
  	interrupt-parent = <&icu0>;
  	interrupts = <112 113 114>;
  };
+
+asc0: serial@600000 {
+	compatible = "lantiq,asc";
+	reg = <0x600000 0x100000>;
1MB of address space? That wastes a lot of virtual space on 32-bit
systems. Just make the size the actual used range.
The size of address space will be updated to the actual used range.
+	interrupt-parent = <&gic>;
+	interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
+	<GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
+	<GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&pll0aclk SSX4_CLK>, <&clkgate1 GATE_URT_CLK>;
+	clock-names = "freq", "asc";
+};

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