RE: [PATCH v1 0/4] add mailbox support for i.MX7D

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Hi Robert,

Thanks for the forwarding.

> -----Original Message-----
> From: Robert Schwebel [mailto:r.schwebel@xxxxxxxxxxxxxx]
> Sent: Friday, June 1, 2018 4:34 PM
> To: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
> Cc: Shawn Guo <shawnguo@xxxxxxxxxx>; Fabio Estevam
> <fabio.estevam@xxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>; Mark
> Rutland <mark.rutland@xxxxxxx>; linux-clk@xxxxxxxxxxxxxxx; linux-arm-
> kernel@xxxxxxxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; A.s. Dong <aisheng.dong@xxxxxxx>; dl-linux-
> imx <linux-imx@xxxxxxx>
> Subject: Re: [PATCH v1 0/4] add mailbox support for i.MX7D
> 
> On Fri, Jun 01, 2018 at 08:58:17AM +0200, Oleksij Rempel wrote:
> > This patches are providing support for mailbox (Messaging Unit) for
> > i.MX7D. Functionality was tested on PHYTEC phyBOARD-Zeta i.MX7D with
> > Linux running on all cores: ARM Cortex-A7 and ARM Cortex-M4.
> >

Thanks for the patch.

> > Both parts of i.MX messaging Unit are visible for all CPUs available
> > on i.MX7D. Communication worked independent of MU side in
> combination
> > with CPU. For example MU-A used on ARM Cortex-A7 and MU-B used on
> ARM
> > Cortex-M4 or other ways around.
> >
> > The question to NXP developers: are there are limitations or
> > recommendations about MU vs CPU combination? The i.MX7D
> documentation
> > talks about "Processor A" and "Processor B". It is not quite clear
> > what processor it actually is (A7 or M4).

The MU vs CPU combination usually are defined by HW design.
It, MU Side A/B,  can either be used by both CPU (A core and M core)
or fixed to one side.
For MX7D case, both side memory map can be accessed by both CPU
Including Interrupt signals. But the recommendation is A core using
MU side A and M core using MU side B.

Regards
Dong Aisheng

> 
> Adding Dong Aisheng and NXP linux team to Cc:.
> 
> rsc
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