Hi Stephen, On 5/30/2018 9:25 PM, Stephen Boyd wrote: > Quoting Sricharan R (2018-05-24 22:40:11) >> Hi Bjorn, >> >> On 5/24/2018 11:09 PM, Bjorn Andersson wrote: >>> On Tue 06 Mar 06:38 PST 2018, Sricharan R wrote: >>> >>>> From: Stephen Boyd <sboyd@xxxxxxxxxxxxxx> >>>> >>>> Krait CPUs have a handful of L2 cache controller registers that >>>> live behind a cp15 based indirection register. First you program >>>> the indirection register (l2cpselr) to point the L2 'window' >>>> register (l2cpdr) at what you want to read/write. Then you >>>> read/write the 'window' register to do what you want. The >>>> l2cpselr register is not banked per-cpu so we must lock around >>>> accesses to it to prevent other CPUs from re-pointing l2cpdr >>>> underneath us. >>>> >>>> Cc: Mark Rutland <mark.rutland@xxxxxxx> >>>> Cc: Russell King <linux@xxxxxxxxxxxxxxxx> >>>> Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx> >>> >>> This should have your signed-off-by here as well. >>> >> >> ok. >> >>> Apart from that: >>> >>> Acked-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxx> >>> >> > > Will these patches come around again? I'll do a quick sweep on them > today but I expect them to be resent. Sure, i will have to resend them again, fixing couple of Bjorn's minor comments. Will address your comments that you would give as well along with that. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
