On Thu, 24 May 2018 13:00:41 +0200 Stefan Agner <stefan@xxxxxxxx> wrote: > > > > > Note that we're in fact using this patch set in Linux today, but > > we had to remove the oobsize inference part. Currently we're > > simply hard coding it to CFG_TVAL_4, but maybe it would be > > cleaner to add ECC algo as a board config instead, e.g. in the > > .dts file or whatever. This seems to be done by other vendors > > already, see for example excerpt of > > Documentation/devicetree/bindings/mtd/gpmc-nand.txt below: > > > > - ti,nand-ecc-opt: A string setting the ECC layout to use. One of: > > "sw" 1-bit Hamming ecc code via software > > "hw" <deprecated> use "ham1" instead > > "hw-romcode" <deprecated> use "ham1" instead > > "ham1" 1-bit Hamming ecc code > > "bch4" 4-bit BCH ecc code > > "bch8" 8-bit BCH ecc code > > "bch16" 16-bit BCH ECC code > > Refer below "How to select correct ECC scheme for your device ?" > > > > It seems as if this method would be equally applicable to Tegra NAND. > > Yeah, ideally we can reuse "nand-ecc-algo". Although, Reed-Solomon is > not yet in the list. So using this property would require to extend > this standard property. I'm okay with that ;-). -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
