On Mon, May 14, 2018 at 11:16:09PM +0200, Enric Balletbo i Serra wrote: > From: Lin Huang <hl@xxxxxxxxxxxxxx> > > These are required to support DDR DVFS on rk3399 platform. The patch also > introduces two new files (rk3399-dram.h and rk3399-dram-default-timing) > with default DRAM settings. > > Signed-off-by: Lin Huang <hl@xxxxxxxxxxxxxx> > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@xxxxxxxxxxxxx> > --- > > .../rockchip/rk3399-dram-default-timing.dtsi | 38 ++++++++++ > arch/arm64/boot/dts/rockchip/rk3399-dram.h | 73 +++++++++++++++++++ > .../boot/dts/rockchip/rk3399-op1-opp.dtsi | 29 ++++++++ > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 +++++ > 4 files changed, 160 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-dram-default-timing.dtsi > create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-dram.h > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-dram-default-timing.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-dram-default-timing.dtsi > new file mode 100644 > index 000000000000..4dfe3e1d8bdf > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3399-dram-default-timing.dtsi > @@ -0,0 +1,38 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR X11) > +/* > + * Copyright (c) 2016-2018, Fuzhou Rockchip Electronics Co., Ltd > + * > + * Author: Lin Huang <hl@xxxxxxxxxxxxxx> > + */ > + > +#include "rk3399-dram.h" > + > +rockchip,ddr3_speed_bin = <21>; > +rockchip,pd_idle = <0x40>; > +rockchip,sr_idle = <0x2>; Don't do includes this way please. These should go under a node. > +rockchip,sr_mc_gate_idle = <0x3>; > +rockchip,srpd_lite_idle = <0x4>; > +rockchip,standby_idle = <0x2000>; > +rockchip,dram_dll_dis_freq = <300000000>; > +rockchip,phy_dll_dis_freq = <125000000>; > +rockchip,auto_pd_dis_freq = <666000000>; > +rockchip,ddr3_odt_dis_freq = <333000000>; > +rockchip,ddr3_drv = <DDR3_DS_40ohm>; > +rockchip,ddr3_odt = <DDR3_ODT_120ohm>; > +rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>; > +rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>; > +rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>; > +rockchip,lpddr3_odt_dis_freq = <333000000>; > +rockchip,lpddr3_drv = <LP3_DS_34ohm>; > +rockchip,lpddr3_odt = <LP3_ODT_240ohm>; > +rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>; > +rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>; > +rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>; > +rockchip,lpddr4_odt_dis_freq = <333000000>; > +rockchip,lpddr4_drv = <LP4_PDDS_60ohm>; > +rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>; > +rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>; > +rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>; > +rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>; > +rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>; > +rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>; -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
