Hi Yong, On Tue, Mar 06, 2018 at 09:51:10AM +0800, Yong Deng wrote: > This patchset add initial support for Allwinner V3s CSI. > > Allwinner V3s SoC features two CSI module. CSI0 is used for MIPI CSI-2 > interface and CSI1 is used for parallel interface. This is not > documented in datasheet but by test and guess. > > This patchset implement a v4l2 framework driver and add a binding > documentation for it. > > Currently, the driver only support the parallel interface. And has been > tested with a BT1120 signal which generating from FPGA. The following > fetures are not support with this patchset: > - ISP > - MIPI-CSI2 > - Master clock for camera sensor > - Power regulator for the front end IC Do you plan on sending another version some time soon? It would be awesome to have this in 4.18. Thanks! Maxime -- Maxime Ripard, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
