On Sun, Apr 22, 2018 at 12:53 PM, Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> wrote: > These are only available on the Meson8m2 SoC (which uses the same > DesignWare Ethernet MAC as Meson8b). > The "eth_tx_clk_50m" signal either provides a 50MHz clock for the RMII > PHYs or the RGMII TX clock (as far as we know the frequency is > controlled by the PRG_ETHERNET registers in the Ethernet MAC "glue" IP > block). > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@xxxxxxxxxxxxxx> Patch applied with Kevin's ACK. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
