Yixun Lan <yixun.lan@xxxxxxxxxxx> writes:
> The ao_clk81 in AO domain have two clock source,
> one from a 32K alt crystal we name it as ao_alt_clk,
> another is the clk81 signal from EE domain.
>
> Acked-by: Jerome Brunet <jbrunet@xxxxxxxxxxxx>
> Signed-off-by: Yixun Lan <yixun.lan@xxxxxxxxxxx>
As this one is a stanadlone, I've applied it to v4.18/dt64,
Thanks,
Kevin
> ---
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index b0eff7d7f771..40ca49fb94a6 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -108,6 +108,13 @@
> #clock-cells = <0>;
> };
>
> + ao_alt_xtal: ao_alt_xtal-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000000>;
> + clock-output-names = "ao_alt_xtal";
> + #clock-cells = <0>;
> + };
> +
> soc {
> compatible = "simple-bus";
> #address-cells = <2>;
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