Hi, On Thu, Apr 26, 2018 at 5:05 AM, Thierry Reding <thierry.reding@xxxxxxxxx> wrote: > If you've got an EDID you should be relying on the EDID to provide the > timings. No need to have any timings in the DT in that case. The problem that's specifically trying to be solved by Sean's series is when we have to use timings other than the one suggested by the EDID. Specifically: * On many Rockchip SoCs there is only one "extra" PLL available. This extra PLL can only be used by one of the two displays (eDP for internal panel or HDMI/DP for external display). The other display has to use one of the "shared" PLLs in the system. These PLLs have their rate set at boot and aren't changed. * In order to provide maximum flexibility to connect external displays, we always want the "extra" PLL dedicated to the external display port. Then we can make lots of pixel clocks. * We work with device and display manufacturers to figure out a pixel clock that is achievable with the shared PLLs and that has valid timings. This is the the pixel clock that was used when testing EMI, etc. It is the one that should be used. * Panel manufacturers agreed that this pixel clock was good to use, but we didn't get an updated EDID that suggested this mode. It's my understanding that panels were already available and it didn't really make sense to program in an EDID to work around a certain board. -Doug -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
