Define the Lager board dependent part of the Ether device node. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx> --- Changes in version 2: - moved PHY pin node phandle from PHY device node to the Ether device node, thus removing all pin control properties from the PHY node; - resolved reject. arch/arm/boot/dts/r8a7790-lager.dts | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) Index: renesas/arch/arm/boot/dts/r8a7790-lager.dts =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7790-lager.dts +++ renesas/arch/arm/boot/dts/r8a7790-lager.dts @@ -1,7 +1,8 @@ /* * Device Tree Source for the Lager board * - * Copyright (C) 2013 Renesas Solutions Corp. + * Copyright (C) 2013-2014 Renesas Solutions Corp. + * Copyright (C) 2014 Cogent Embedded, Inc. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -124,6 +125,16 @@ renesas,function = "scif0"; }; + ether_pins: ether { + renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; + renesas,function = "eth"; + }; + + phy1_pins: phy1 { + renesas,groups = "intc_irq0"; + renesas,function = "intc"; + }; + scif1_pins: serial1 { renesas,groups = "scif1_data"; renesas,function = "scif1"; @@ -150,6 +161,21 @@ }; }; +ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "ok"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + &mmcif1 { pinctrl-0 = <&mmc1_pins>; pinctrl-names = "default"; -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html