Hi Philippe, On Thursday, 19 April 2018 12:46:31 EEST Philippe CORNU wrote: > On 04/19/2018 10:20 AM, Laurent Pinchart wrote: > > On Tuesday, 10 April 2018 08:19:27 EEST Philippe Cornu wrote: > > > >> Add the 3 optional power supplies using the exact description > >> found in the document named > >> "SiI9022A/SiI9024A HDMI Transmitter Data Sheet (August 2016)". > >> > >> Signed-off-by: Philippe Cornu <philippe.cornu@xxxxxx> > >> --- > >> drivers/gpu/drm/bridge/sii902x.c | 39 +++++++++++++++++++++++++++++++---- > >> 1 file changed, 35 insertions(+), 4 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/bridge/sii902x.c > >> b/drivers/gpu/drm/bridge/sii902x.c index 60373d7eb220..e17ba6db1ec8 > >> 100644 > >> --- a/drivers/gpu/drm/bridge/sii902x.c > >> +++ b/drivers/gpu/drm/bridge/sii902x.c [snip] > >> @@ -443,6 +471,9 @@ static int sii902x_remove(struct i2c_client *client) > >> > >> drm_bridge_remove(&sii902x->bridge); > >> > >> + regulator_bulk_disable(ARRAY_SIZE(sii902x->supplies), > >> + sii902x->supplies); > >> + > > > > While this seems functionally correct, would it be useful to only enable > > power supplies when needed to save power ? > that is a good point. I do not know well (yet) this bridge. Maybe I can > add a 3rd patch with bridge pre_enable() and post_disable() containing > reset & supplies management. Or I can put reset&supplies in bridge > enable() & disable() but it could be a little messy. > > Any opinion/advice? I'm not familiar with this bridge yet, so we need to be careful. The first point you need to check is the hardware requirements regarding power supply sequencing. For instance could it damage the chip if the I/O supply is turned off while the I/O pins are externally driven ? Can the core supplies be turned off with the I/O supply on ? Then, based on the hardware limitations, you should pick the appropriate location for power handling. > >> return 0; > >> } -- Regards, Laurent Pinchart -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
