Hi Yisheng, Sorry, I think we missed your question here. On Wed, Mar 28, 2018 at 3:12 PM Yisheng Xie <xieyisheng1@xxxxxxxxxx> wrote: > Hi Vivek, > On 2018/3/28 12:37, Vivek Gautam wrote: > > Hi Yisheng > > > > > > On 3/28/2018 6:54 AM, Yisheng Xie wrote: > >> Hi Vivek, > >> > >> On 2018/3/13 16:55, Vivek Gautam wrote: > >>> +- power-domains: Specifiers for power domains required to be powered on for > >>> + the SMMU to operate, as per generic power domain bindings. > >>> + > >> In this patchset, power-domains is not used right? And you just do the clock gating, > >> but not power gating, right? > > > > We are handling the power-domains too. Please see the example in this binding doc. > I see, but I do not find the point in code of these patchset, do you mean PMIC(e.g mmcc) > will gate the power domain of SMMU(e.g. MDSS_GDSC of mmcc) when PMIC suspend? If respective SoC power domains is registered as a standard genpd PM domain, then the runtime PM subsystem will take care of power domain control at runtime suspend and resume. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
