On Tue, Mar 27, 2018 at 8:15 AM, liwei (CM) <liwei213@xxxxxxxxxx> wrote:
> Hi, Arnd
>
> At present our ufs module mainly has four clocks from the outside:
> hclk_ufs: main clock of ufs controller ,freq is 207.5MHz
> cfg_phy_clk: configuration clock of MPHY, freq is 51.875MHz
> ref_phy_clk: reference clock of MPHY from PMU, freq is 19.2MHz
> ref_io_clk: reference clock for the external interface to the device, freq is 19.2MHz
>
> We control two clocks "ref_io_clk" and "cfg_phy_clk" in the driver because the other
> two are controlled by main clock module and pmu.
I'm not completely sure what you mean with "control" here. Do you mean
setting the
rate and disabling them during runtime power management? What does it mean for
the clock to be controlled by teh "main clock module and pmu"?
> for this patch, cfg_phy_clk corresponds to "phy_clk", ref_io_clk corresponds to "ref_clk".
I'm not sure I understand the difference between ref_phy_clk and
ref_io_clk, but it sounds
like we should give both of those names in the ufs-platform binding.
Your hclk_ufs would appear to correspond to what qualcomm calls core_clk, so
maybe use that name as well.
cfg_phy_clk seems to be something that qcom would not have, but it's
also generic
enough to list it in the common binding.
> So the clks in the patch you give appear to be unsuitable for describing this .And the following clks of qcom are internal clock?
> We didn't describe or pay attention to the clock inside the ufs module.
>
> PHY to controller symbol synchronization clocks:
> "rx_lane0_sync_clk" - RX Lane 0
> "rx_lane1_sync_clk" - RX Lane 1
> "tx_lane0_sync_clk" - TX Lane 0
> "tx_lane1_sync_clk" - TX Lane 1
Right, let's leave those for the qcom private binding.
Arnd
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