On Tue, 2018-03-27 at 12:06 +0000, Prabhakar Kushwaha wrote: > Hi Boris, > > > -----Original Message----- > > From: Boris Brezillon [mailto:boris.brezillon@xxxxxxxxxxx] > > Sent: Friday, March 23, 2018 2:04 PM > > To: Prabhakar Kushwaha <prabhakar.kushwaha@xxxxxxx>; > > robh@xxxxxxxxxx > > Cc: linux-mtd@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; > > mark.rutland@xxxxxxx; shawnguo@xxxxxxxxxx; boris.brezillon@free- > > electrons.com; computersforpeace@xxxxxxxxx; oss@xxxxxxxxxxxx; Leo Li > > <leoyang.li@xxxxxxx>; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > > Subject: Re: [PATCH 1/2][v6] dt-bindings: mtd-physmap: Add endianness > > supports > > > > You still haven't answered the comments I made on your v5. To me, this > > does > > not represent how the controller and chip pins are connected, but how the > > chip was programmed and which endianness should be used by the > > controller to correctly read the data back. Maybe I'm wrong, hence my > > question. > > > > NXP's ARM SoC has IFC module which interface with NOR flash. Here IFC is big > endian module connected with NOR flash. > As SoC has ARM processor(Littler Endian), CONFIG_MTD_CFI_BE_BYTE_SWAP needs > to be enabled to make sure data is read correctly. > This is the reason, I wrote about connection between controller and flash. > > In a way, I agree with you. It is not about connection. > It is about how controller read the data (inherently ARM processor) It is not about anything inherent to ARM (which, like PPC, is a bi-endian arch). It's about the programming model of IFC on certain SoCs. -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
