Manu On Thu, Mar 22, 2018 at 11:11 PM, Manu Gautam <mgautam@xxxxxxxxxxxxxx> wrote: > QMP PHY for USB mode requires pipe_clk for calibration and PLL lock > to take place. This clock is output from PHY to GCC clock_ctl and then > fed back to QMP PHY and is available from PHY only after PHY is reset > and initialized, hence it can't be enabled too early in initialization > sequence. > > Signed-off-by: Manu Gautam <mgautam@xxxxxxxxxxxxxx> > --- > drivers/phy/qualcomm/phy-qcom-qmp.c | 33 ++++++++++++++++++++++++++++++++- > 1 file changed, 32 insertions(+), 1 deletion(-) So it's now new with this patch, but it's more obvious with this patch. It seems like "UFS/PCIE" is kinda broken w/ respect to how it controls its clock. Specifically: * If you init the PHY but don't power it on, then you "exit" the PHY: you'll disable/unprepare "pipe_clk" even though you never prepare/enabled it. * If you init the PHY, power it on, power it off, power it on, and exit the PHY: you'll leave the clock prepared one extra time. Specifically I'd expect: for UFS/PCIE the disable/unprepare should be symmetric with the enable/prepare and should be in "power off", not in exit. ...or did I miss something? Interestingly, your patch fixes this problem for USB3 (where init/exit are now symmetric), but leaves the problem there for UFS/PCIE. -Doug -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
