Quoting David Lechner (2018-03-15 19:52:17) > This adds a new binding for the PLL IP blocks in the mach-davinci > family of processors. Currently, only da850 has device tree support > but these bindings can also work for other SoCs in this family just > by adding new compatible strings. > > Note: Although these PLL controllers are very similar to the TI Keystone > SoCs, we are not re-using those bindings. The Keystone bindings use a > legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs > have a slightly different PLL register layout and a number of quirks > that can't be handled by the existing bindings, so the keystone bindings > could not be used as-is anyway. > > Signed-off-by: David Lechner <david@xxxxxxxxxxxxxx> > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > --- Applied to clk-next -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
