Hi, On 16/03/18 14:02, Icenowy Zheng wrote: > The Allwinner H6 SoC has two pin controllers, one main controller > (called CPUX-PORT in user manual) and one controller in CPUs power > domain (called CPUS-PORT in user manual). > > This commit introduces support for the main pin controller on H6. > > The pin bank A and B are not wired out and hidden from the SoC's > documents, however it's shown that the "ATE" (an AC200 chip > co-packaged with the H6 die) is connected to the main SoC die via these > pin banks. The information about these banks is just copied from the BSP > pinctrl driver, but re-formatted to fit the mainline pinctrl driver > format. The GPIO functions are dropped, as they're impossible to use -- > except a GPIO&IRQ only pin (PB20) which might be the IRQ of ATE. > > Signed-off-by: Icenowy Zheng <icenowy@xxxxxxx> > Acked-by: Rob Herring <robh@xxxxxxxxxx> As mentioned before, I checked every single pin against the manual and this looks correct to me. Reviewed-by: Andre Przywara <andre.przywara@xxxxxxx> Thanks! Andre. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
