Remove DT entries of hw block offsets and other target specific catalog
information for SDM845.
Signed-off-by: Sravanthi Kollukuduru <skolluku@xxxxxxxxxxxxxx>
---
.../devicetree/bindings/display/msm/dpu.txt | 530 ---------------------
1 file changed, 530 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt
index 136f0d3..90cd3e0 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -19,61 +19,6 @@ Required properties
- interrupt-controller: Mark the device node as an interrupt controller.
- #interrupt-cells: Should be one. The first cell is interrupt number.
- iommus: Specifies the SID's used by this context bank.
-- qcom,dpu-sspp-type: Array of strings for DPU source surface pipes type information.
- A source pipe can be "vig", "rgb", "dma" or "cursor" type.
- Number of xin ids defined should match the number of offsets
- defined in property: qcom,dpu-sspp-off.
-- qcom,dpu-sspp-off: Array of offset for DPU source surface pipes. The offsets
- are calculated from register "mdp_phys" defined in
- reg property + "dpu-off". The number of offsets defined here should
- reflect the amount of pipes that can be active in DPU for
- this configuration.
-- qcom,dpu-sspp-xin-id: Array of VBIF clients ids (xins) corresponding
- to the respective source pipes. Number of xin ids
- defined should match the number of offsets
- defined in property: qcom,dpu-sspp-off.
-- qcom,dpu-ctl-off: Array of offset addresses for the available ctl
- hw blocks within DPU, these offsets are
- calculated from register "mdp_phys" defined in
- reg property. The number of ctl offsets defined
- here should reflect the number of control paths
- that can be configured concurrently on DPU for
- this configuration.
-- qcom,dpu-wb-off: Array of offset addresses for the programmable
- writeback blocks within DPU.
-- qcom,dpu-wb-xin-id: Array of VBIF clients ids (xins) corresponding
- to the respective writeback. Number of xin ids
- defined should match the number of offsets
- defined in property: qcom,dpu-wb-off.
-- qcom,dpu-mixer-off: Array of offset addresses for the available
- mixer blocks that can drive data to panel
- interfaces. These offsets are be calculated from
- register "mdp_phys" defined in reg property.
- The number of offsets defined should reflect the
- amount of mixers that can drive data to a panel
- interface.
-- qcom,dpu-dspp-top-off: Offset address for the dspp top block.
- The offset is calculated from register "mdp_phys"
- defined in reg property.
-- qcom,dpu-dspp-off: Array of offset addresses for the available dspp
- blocks. These offsets are calculated from
- register "mdp_phys" defined in reg property.
-- qcom,dpu-pp-off: Array of offset addresses for the available
- pingpong blocks. These offsets are calculated
- from register "mdp_phys" defined in reg property.
-- qcom,dpu-pp-slave: Array of flags indicating whether each ping pong
- block may be configured as a pp slave.
-- qcom,dpu-intf-off: Array of offset addresses for the available DPU
- interface blocks that can drive data to a
- panel controller. The offsets are calculated
- from "mdp_phys" defined in reg property. The number
- of offsets defined should reflect the number of
- programmable interface blocks available in hardware.
-- qcom,dpu-mixer-blend-op-off Array of offset addresses for the available
- blending stages. The offsets are relative to
- qcom,dpu-mixer-off.
-- qcom,dpu-mixer-pair-mask Array of mixer numbers that can be paired with
- mixer number corresponding to the array index.
Optional properties:
- clock-rate: List of clock rates in Hz.
@@ -93,182 +38,6 @@ Optional properties:
-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
-- qcom,dpu-sspp-src-size: A u32 value indicates the address range for each sspp.
-- qcom,dpu-mixer-size: A u32 value indicates the address range for each mixer.
-- qcom,dpu-ctl-size: A u32 value indicates the address range for each ctl.
-- qcom,dpu-dspp-size: A u32 value indicates the address range for each dspp.
-- qcom,dpu-intf-size: A u32 value indicates the address range for each intf.
-- qcom,dpu-dsc-size: A u32 value indicates the address range for each dsc.
-- qcom,dpu-cdm-size: A u32 value indicates the address range for each cdm.
-- qcom,dpu-pp-size: A u32 value indicates the address range for each pingpong.
-- qcom,dpu-wb-size: A u32 value indicates the address range for each writeback.
-- qcom,dpu-len: A u32 entry for DPU address range.
-- qcom,dpu-intf-max-prefetch-lines: Array of u32 values for max prefetch lines on
- each interface.
-- qcom,dpu-sspp-linewidth: A u32 value indicates the max sspp line width.
-- qcom,dpu-mixer-linewidth: A u32 value indicates the max mixer line width.
-- qcom,dpu-wb-linewidth: A u32 value indicates the max writeback line width.
-- qcom,dpu-sspp-scale-size: A u32 value indicates the scaling block size on sspp.
-- qcom,dpu-mixer-blendstages: A u32 value indicates the max mixer blend stages for
- alpha blending.
-- qcom,dpu-qseed-type: A string entry indiates qseed support on sspp and wb.
- It supports "qssedv3" and "qseedv2" entries for qseed
- type. By default "qseedv2" is used if this optional property
- is not defined.
-- qcom,dpu-csc-type: A string entry indicates csc support on sspp and wb.
- It supports "csc" and "csc-10bit" entries for csc
- type.
-- qcom,dpu-highest-bank-bit: A u32 property to indicate GPU/Camera/Video highest memory
- bank bit used for tile format buffers.
-- qcom,dpu-ubwc-version: Property to specify the UBWC feature version.
-- qcom,dpu-ubwc-static: Property to specify the default UBWC static
- configuration value.
-- qcom,dpu-ubwc-swizzle: Property to specify the default UBWC swizzle
- configuration value.
-- qcom,dpu-panic-per-pipe: Boolean property to indicate if panic signal
- control feature is available on each source pipe.
-- qcom,dpu-has-src-split: Boolean property to indicate if source split
- feature is available or not.
-- qcom,dpu-has-dim-layer: Boolean property to indicate if mixer has dim layer
- feature is available or not.
-- qcom,dpu-has-idle-pc: Boolean property to indicate if target has idle
- power collapse feature available or not.
-- qcom,dpu-has-mixer-gc: Boolean property to indicate if mixer has gamma correction
- feature available or not.
-- qcom,dpu-has-dest-scaler: Boolean property to indicate if destination scaler
- feature is available or not.
-- qcom,dpu-max-dest-scaler-input-linewidth: A u32 value indicates the
- maximum input line width to destination scaler.
-- qcom,dpu-max-dest-scaler-output-linewidth: A u32 value indicates the
- maximum output line width of destination scaler.
-- qcom,dpu-dest-scaler-top-off: A u32 value provides the
- offset from mdp base to destination scaler block.
-- qcom,dpu-dest-scaler-top-size: A u32 value indicates the address range for ds top
-- qcom,dpu-dest-scaler-off: Array of u32 offsets indicate the qseed3 scaler blocks
- offset from destination scaler top offset.
-- qcom,dpu-dest-scaler-size: A u32 value indicates the address range for each scaler block
-- qcom,dpu-sspp-clk-ctrl: Array of offsets describing clk control
- offsets for dynamic clock gating. 1st value
- in the array represents offset of the control
- register. 2nd value represents bit offset within
- control register. Number of offsets defined should
- match the number of offsets defined in
- property: qcom,dpu-sspp-off
-- qcom,dpu-sspp-clk-status: Array of offsets describing clk status
- offsets for dynamic clock gating. 1st value
- in the array represents offset of the status
- register. 2nd value represents bit offset within
- control register. Number of offsets defined should
- match the number of offsets defined in
- property: qcom,dpu-sspp-off.
-- qcom,dpu-sspp-excl-rect: Array of u32 values indicating exclusion rectangle
- support on each sspp.
-- qcom,dpu-sspp-smart-dma-priority: Array of u32 values indicating hw pipe
- priority of secondary rectangles when smart dma
- is supported. Number of priority values should
- match the number of offsets defined in
- qcom,dpu-sspp-off node. Zero indicates no support
- for smart dma for the sspp.
-- qcom,dpu-smart-dma-rev: A string entry indicating the smart dma version
- supported on the device. Supported entries are
- "smart_dma_v1" and "smart_dma_v2".
-- qcom,dpu-intf-type: Array of string provides the interface type information.
- Possible string values
- "dsi" - dsi display interface
- "dp" - Display Port interface
- "hdmi" - HDMI display interface
- An interface is considered as "none" if interface type
- is not defined.
-- qcom,dpu-off: DPU offset from "mdp_phys" defined in reg property.
-- qcom,dpu-cdm-off: Array of offset addresses for the available
- cdm blocks. These offsets will be calculated from
- register "mdp_phys" defined in reg property.
-- qcom,dpu-vbif-off: Array of offset addresses for the available
- vbif blocks. These offsets will be calculated from
- register "vbif_phys" defined in reg property.
-- qcom,dpu-vbif-size: A u32 value indicates the vbif block address range.
-- qcom,dpu-te-off: A u32 offset indicates the te block offset on pingpong.
- This offset is 0x0 by default.
-- qcom,dpu-te2-off: A u32 offset indicates the te2 block offset on pingpong.
-- qcom,dpu-te-size: A u32 value indicates the te block address range.
-- qcom,dpu-te2-size: A u32 value indicates the te2 block address range.
-- qcom,dpu-dsc-off: A u32 offset indicates the dsc block offset on pingpong.
-- qcom,dpu-dither-off: A u32 offset indicates the dither block offset on pingpong.
-- qcom,dpu-dither-version: A u32 value indicates the dither block version.
-- qcom,dpu-dither-size: A u32 value indicates the dither block address range.
-- qcom,dpu-sspp-vig-blocks: A node that lists the blocks inside the VIG hardware. The
- block entries will contain the offset and version (if needed)
- of each feature block. The presence of a block entry
- indicates that the SSPP VIG contains that feature hardware.
- e.g. qcom,dpu-sspp-vig-blocks
- -- qcom,dpu-vig-csc-off: offset of CSC hardware
- -- qcom,dpu-vig-qseed-off: offset of QSEED hardware
- -- qcom,dpu-vig-qseed-size: A u32 address range for qseed scaler.
- -- qcom,dpu-vig-pcc: offset and version of PCC hardware
- -- qcom,dpu-vig-hsic: offset and version of global PA adjustment
- -- qcom,dpu-vig-memcolor: offset and version of PA memcolor hardware
-- qcom,dpu-sspp-rgb-blocks: A node that lists the blocks inside the RGB hardware. The
- block entries will contain the offset and version (if needed)
- of each feature block. The presence of a block entry
- indicates that the SSPP RGB contains that feature hardware.
- e.g. qcom,dpu-sspp-vig-blocks
- -- qcom,dpu-rgb-scaler-off: offset of RGB scaler hardware
- -- qcom,dpu-rgb-scaler-size: A u32 address range for scaler.
- -- qcom,dpu-rgb-pcc: offset and version of PCC hardware
-- qcom,dpu-dspp-blocks: A node that lists the blocks inside the DSPP hardware. The
- block entries will contain the offset and version of each
- feature block. The presence of a block entry indicates that
- the DSPP contains that feature hardware.
- e.g. qcom,dpu-dspp-blocks
- -- qcom,dpu-dspp-pcc: offset and version of PCC hardware
- -- qcom,dpu-dspp-gc: offset and version of GC hardware
- -- qcom,dpu-dspp-igc: offset and version of IGC hardware
- -- qcom,dpu-dspp-hsic: offset and version of global PA adjustment
- -- qcom,dpu-dspp-memcolor: offset and version of PA memcolor hardware
- -- qcom,dpu-dspp-sixzone: offset and version of PA sixzone hardware
- -- qcom,dpu-dspp-gamut: offset and version of Gamut mapping hardware
- -- qcom,dpu-dspp-dither: offset and version of dither hardware
- -- qcom,dpu-dspp-hist: offset and version of histogram hardware
- -- qcom,dpu-dspp-vlut: offset and version of PA vLUT hardware
-- qcom,dpu-mixer-blocks: A node that lists the blocks inside the layer mixer hardware. The
- block entries will contain the offset and version (if needed)
- of each feature block. The presence of a block entry
- indicates that the layer mixer contains that feature hardware.
- e.g. qcom,dpu-mixer-blocks
- -- qcom,dpu-mixer-gc: offset and version of mixer GC hardware
-- qcom,dpu-dspp-ad-off: Array of u32 offsets indicate the ad block offset from the
- DSPP offset. Since AD hardware is represented as part of
- DSPP block, the AD offsets must be offset from the
- corresponding DSPP base.
-- qcom,dpu-dspp-ad-version A u32 value indicating the version of the AD hardware
-- qcom,dpu-vbif-id: Array of vbif ids corresponding to the
- offsets defined in property: qcom,dpu-vbif-off.
-- qcom,dpu-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit
-- qcom,dpu-vbif-default-ot-wr-limit: A u32 value indicates the default write OT limit
-- qcom,dpu-vbif-dynamic-ot-rd-limit: A series of 2 cell property, with a format
- of (pps, OT limit), where pps is pixel per second and
- OT limit is the read limit to apply if the given
- pps is not exceeded.
-- qcom,dpu-vbif-dynamic-ot-wr-limit: A series of 2 cell property, with a format
- of (pps, OT limit), where pps is pixel per second and
- OT limit is the write limit to apply if the given
- pps is not exceeded.
-- qcom,dpu-vbif-memtype-0: Array of u32 vbif memory type settings, group 0
-- qcom,dpu-vbif-memtype-1: Array of u32 vbif memory type settings, group 1
-- qcom,dpu-wb-id: Array of writeback ids corresponding to the
- offsets defined in property: qcom,dpu-wb-off.
-- qcom,dpu-wb-clk-ctrl: Array of 2 cell property describing clk control
- offsets for dynamic clock gating. 1st value
- in the array represents offset of the control
- register. 2nd value represents bit offset within
- control register. Number of offsets defined should
- match the number of offsets defined in
- property: qcom,dpu-wb-off
-- qcom,dpu-reg-dma-off: Offset of the register dma hardware block from
- "regdma_phys" defined in reg property.
-- qcom,dpu-reg-dma-version: Version of the reg dma hardware block.
-- qcom,dpu-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys"
- defined in reg property.
- qcom,dpu-dram-channels: This represents the number of channels in the
Bus memory controller.
- qcom,dpu-num-nrt-paths: Integer property represents the number of non-realtime
@@ -277,95 +46,6 @@ Optional properties:
for particular chipset.
These paths must be defined after rt-paths in
"qcom,msm-bus,vectors-KBps" vector request.
-- qcom,dpu-max-bw-low-kbps: This value indicates the max bandwidth in Kbps
- that can be supported without underflow.
- This is a low bandwidth threshold which should
- be applied in most scenarios to be safe from
- underflows when unable to satisfy bandwidth
- requirements.
-- qcom,dpu-max-bw-high-kbps: This value indicates the max bandwidth in Kbps
- that can be supported without underflow.
- This is a high bandwidth threshold which can be
- applied in scenarios where panel interface can
- be more tolerant to memory latency such as
- command mode panels.
-- qcom,dpu-core-ib-ff: A string entry indicating the fudge factor for
- core ib calculation.
-- qcom,dpu-core-clk-ff: A string entry indicating the fudge factor for
- core clock calculation.
-- qcom,dpu-min-core-ib-kbps: This u32 value indicates the minimum mnoc ib
- vote in Kbps that can be reduced without hitting underflow.
- BW calculation logic will choose the IB bandwidth requirement
- based on usecase if this floor value is not defined.
-- qcom,dpu-min-llcc-ib-kbps: This u32 value indicates the minimum llcc ib
- vote in Kbps that can be reduced without hitting underflow.
- BW calculation logic will choose the IB bandwidth requirement
- based on usecase if this floor value is not defined.
-- qcom,dpu-min-dram-ib-kbps: This u32 value indicates the minimum dram ib
- vote in Kbps that can be reduced without hitting underflow.
- BW calculation logic will choose the IB bandwidth requirement
- based on usecase if this floor value is not defined.
-- qcom,dpu-comp-ratio-rt: A string entry indicating the compression ratio
- for each supported compressed format on realtime interface.
- The string is composed of one or more of
- <fourcc code>/<vendor code>/<modifier>/<compression ratio>
- separated with spaces.
-- qcom,dpu-comp-ratio-nrt: A string entry indicating the compression ratio
- for each supported compressed format on non-realtime interface.
- The string is composed of one or more of
- <fourcc code>/<vendor code>/<modifier>/<compression ratio>
- separated with spaces.
-- qcom,dpu-undersized-prefill-lines: A u32 value indicates the size of undersized prefill in lines.
-- qcom,dpu-xtra-prefill-lines: A u32 value indicates the extra prefill in lines.
-- qcom,dpu-dest-scale-prefill-lines: A u32 value indicates the latency of destination scaler in lines.
-- qcom,dpu-macrotile-prefill-lines: A u32 value indicates the latency of macrotile in lines.
-- qcom,dpu-yuv-nv12-prefill-lines: A u32 value indicates the latency of yuv/nv12 in lines.
-- qcom,dpu-linear-prefill-lines: A u32 value indicates the latency of linear in lines.
-- qcom,dpu-downscaling-prefill-lines: A u32 value indicates the latency of downscaling in lines.
-- qcom,dpu-max-per-pipe-bw-kbps: Array of u32 value indicates the max per pipe bandwidth in Kbps.
-- qcom,dpu-amortizable-threshold: This value indicates the min for traffic shaping in lines.
-- qcom,dpu-vbif-qos-rt-remap: This array is used to program vbif qos remapper register
- priority for realtime clients.
-- qcom,dpu-vbif-qos-nrt-remap: This array is used to program vbif qos remapper register
- priority for non-realtime clients.
-- qcom,dpu-danger-lut: A 4 cell property, with a format of <linear,
- tile, nrt, cwb>,
- indicating the danger luts on sspp.
-- qcom,dpu-safe-lut: A 4 cell property, with a format of <linear,
- tile, nrt, cwb>,
- indicating the safe luts on sspp.
-- qcom,dpu-qos-lut-linear: Array of 3 cell property, with a format of
- <fill level, lut hi, lut lo> in ascending fill level
- indicating the qos luts for linear format on sspp.
- Zero fill level on the last entry identifies the default lut.
-- qcom,dpu-qos-lut-macrotile: Array of 3 cell property, with a format of
- <fill level, lut hi, lut lo> in ascending fill level
- indicating the qos luts for macrotile format on sspp.
- Zero fill level on the last entry identifies the default lut.
-- qcom,dpu-qos-lut-nrt: Array of 3 cell property, with a format of
- <fill level, lut hi, lut lo> in ascending fill level
- indicating the qos luts for nrt (e.g wfd) on sspp.
- Zero fill level on the last entry identifies the default lut.
-- qcom,dpu-qos-lut-cwb: Array of 3 cell property, with a format of
- <fill level, lut hi, lut lo> in ascending fill level
- indicating the qos luts for cwb on sspp.
- Zero fill level on the last entry identifies the default lut.
-- qcom,dpu-cdp-setting: Array of 2 cell property, with a format of
- <read enable, write enable> for cdp use cases in
- order of <real_time>, and <non_real_time>.
-- qcom,dpu-inline-rot-xin: An integer array of xin-ids related to inline
- rotation.
-- qcom,dpu-inline-rot-xin-type: A string array indicating the type of xin,
- namely sspp or wb. Number of entries should match
- the number of xin-ids defined in
- property: qcom,dpu-inline-rot-xin
-- qcom,dpu-inline-rot-clk-ctrl: Array of offsets describing clk control
- offsets for dynamic clock gating. 1st value
- in the array represents offset of the control
- register. 2nd value represents bit offset within
- control register. Number of offsets defined should
- match the number of xin-ids defined in
- property: qcom,dpu-inline-rot-xin
Bus Scaling Subnodes:
- qcom,dpu-reg-bus: Property to provide Bus scaling for register access for
@@ -447,223 +127,13 @@ Example:
#interrupt-cells = <1>;
iommus = <&mdp_smmu 0>;
- qcom,dpu-off = <0x1000>;
- qcom,dpu-ctl-off = <0x00002000 0x00002200 0x00002400
- 0x00002600 0x00002800>;
- qcom,dpu-mixer-off = <0x00045000 0x00046000
- 0x00047000 0x0004a000>;
- qcom,dpu-dspp-top-off = <0x1300>;
- qcom,dpu-dspp-off = <0x00055000 0x00057000>;
- qcom,dpu-dspp-ad-off = <0x24000 0x22800>;
- qcom,dpu-dspp-ad-version = <0x00030000>;
- qcom,dpu-dest-scaler-top-off = <0x00061000>;
- qcom,dpu-dest-scaler-off = <0x800 0x1000>;
- qcom,dpu-wb-off = <0x00066000>;
- qcom,dpu-wb-xin-id = <6>;
- qcom,dpu-intf-off = <0x0006b000 0x0006b800
- 0x0006c000 0x0006c800>;
- qcom,dpu-intf-type = "none", "dsi", "dsi", "hdmi";
- qcom,dpu-pp-off = <0x00071000 0x00071800
- 0x00072000 0x00072800>;
- qcom,dpu-pp-slave = <0x0 0x0 0x0 0x0>;
- qcom,dpu-cdm-off = <0x0007a200>;
- qcom,dpu-dsc-off = <0x00081000 0x00081400>;
- qcom,dpu-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;
-
- qcom,dpu-mixer-pair-mask = <2 1 6 0 0 3>;
- qcom,dpu-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
- 0xb0 0xc8 0xe0 0xf8 0x110>;
-
-
- qcom,dpu-sspp-type = "vig", "vig", "vig",
- "vig", "rgb", "rgb",
- "rgb", "rgb", "dma",
- "dma", "cursor", "cursor";
-
- qcom,dpu-sspp-off = <0x00005000 0x00007000 0x00009000
- 0x0000b000 0x00015000 0x00017000
- 0x00019000 0x0001b000 0x00025000
- 0x00027000 0x00035000 0x00037000>;
-
- qcom,dpu-sspp-xin-id = <0 4 8
- 12 1 5
- 9 13 2
- 10 7 7>;
-
- /* offsets are relative to "mdp_phys + qcom,dpu-off */
- qcom,dpu-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
- <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
- <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
- <0x3b0 16>;
- qcom,dpu-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
- <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
- <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
- <0x3b0 16>;
- qcom,dpu-mixer-linewidth = <2560>;
- qcom,dpu-sspp-linewidth = <2560>;
- qcom,dpu-mixer-blendstages = <0x7>;
- qcom,dpu-highest-bank-bit = <0x2>;
- qcom,dpu-ubwc-version = <0x100>;
- qcom,dpu-ubwc-static = <0x100>;
- qcom,dpu-ubwc-swizzle = <0>;
- qcom,dpu-panic-per-pipe;
- qcom,dpu-has-src-split;
- qcom,dpu-has-dim-layer;
- qcom,dpu-sspp-src-size = <0x100>;
- qcom,dpu-mixer-size = <0x100>;
- qcom,dpu-ctl-size = <0x100>;
- qcom,dpu-dspp-top-size = <0xc>;
- qcom,dpu-dspp-size = <0x100>;
- qcom,dpu-intf-size = <0x100>;
- qcom,dpu-dsc-size = <0x100>;
- qcom,dpu-cdm-size = <0x100>;
- qcom,dpu-pp-size = <0x100>;
- qcom,dpu-wb-size = <0x100>;
- qcom,dpu-dest-scaler-top-size = <0xc>;
- qcom,dpu-dest-scaler-size = <0x800>;
- qcom,dpu-len = <0x100>;
- qcom,dpu-wb-linewidth = <2560>;
- qcom,dpu-sspp-scale-size = <0x100>;
- qcom,dpu-mixer-blendstages = <0x8>;
- qcom,dpu-qseed-type = "qseedv2";
- qcom,dpu-csc-type = "csc-10bit";
- qcom,dpu-highest-bank-bit = <15>;
- qcom,dpu-has-mixer-gc;
- qcom,dpu-has-idle-pc;
- qcom,dpu-has-dest-scaler;
- qcom,dpu-max-dest-scaler-input-linewidth = <2048>;
- qcom,dpu-max-dest-scaler-output-linewidth = <2560>;
- qcom,dpu-sspp-max-rects = <1 1 1 1
- 1 1 1 1
- 1 1
- 1 1>;
- qcom,dpu-sspp-excl-rect = <1 1 1 1
- 1 1 1 1
- 1 1
- 1 1>;
- qcom,dpu-sspp-smart-dma-priority = <0 0 0 0
- 0 0 0 0
- 0 0
- 1 2>;
- qcom,dpu-smart-dma-rev = "smart_dma_v2";
- qcom,dpu-te-off = <0x100>;
- qcom,dpu-te2-off = <0x100>;
- qcom,dpu-te-size = <0xffff>;
- qcom,dpu-te2-size = <0xffff>;
-
- qcom,dpu-wb-id = <2>;
- qcom,dpu-wb-clk-ctrl = <0x2bc 16>;
-
- qcom,dpu-danger-lut = <0x0000000f 0x0000ffff 0x00000000
- 0x00000000>;
- qcom,dpu-safe-lut = <0xfffc 0xff00 0xffff 0xffff>;
- qcom,dpu-qos-lut-linear =
- <4 0x00000000 0x00000357>,
- <5 0x00000000 0x00003357>,
- <6 0x00000000 0x00023357>,
- <7 0x00000000 0x00223357>,
- <8 0x00000000 0x02223357>,
- <9 0x00000000 0x22223357>,
- <10 0x00000002 0x22223357>,
- <11 0x00000022 0x22223357>,
- <12 0x00000222 0x22223357>,
- <13 0x00002222 0x22223357>,
- <14 0x00012222 0x22223357>,
- <0 0x00112222 0x22223357>;
- qcom,dpu-qos-lut-macrotile =
- <10 0x00000003 0x44556677>,
- <11 0x00000033 0x44556677>,
- <12 0x00000233 0x44556677>,
- <13 0x00002233 0x44556677>,
- <14 0x00012233 0x44556677>,
- <0 0x00112233 0x44556677>;
- qcom,dpu-qos-lut-nrt =
- <0 0x00000000 0x00000000>;
- qcom,dpu-qos-lut-cwb =
- <0 0x75300000 0x00000000>;
-
- qcom,dpu-cdp-setting = <1 1>, <1 0>;
-
- qcom,dpu-vbif-off = <0 0>;
- qcom,dpu-vbif-id = <0 1>;
- qcom,dpu-vbif-default-ot-rd-limit = <32>;
- qcom,dpu-vbif-default-ot-wr-limit = <16>;
- qcom,dpu-vbif-dynamic-ot-rd-limit = <62208000 2>,
- <124416000 4>, <248832000 16>;
- qcom,dpu-vbif-dynamic-ot-wr-limit = <62208000 2>,
- <124416000 4>, <248832000 16>;
- qcom,dpu-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
- qcom,dpu-vbif-memtype-1 = <3 3 3 3 3 3>;
-
qcom,dpu-dram-channels = <2>;
qcom,dpu-num-nrt-paths = <1>;
- qcom,dpu-max-bw-high-kbps = <9000000>;
- qcom,dpu-max-bw-low-kbps = <9000000>;
-
- qcom,dpu-core-ib-ff = "1.1";
- qcom,dpu-core-clk-ff = "1.0";
- qcom,dpu-min-core-ib-kbps = <2400000>;
- qcom,dpu-min-llcc-ib-kbps = <800000>;
- qcom,dpu-min-dram-ib-kbps = <800000>;
- qcom,dpu-comp-ratio-rt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3";
- qcom,dpu-comp-ratio-nrt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3";
- qcom,dpu-undersized-prefill-lines = <4>;
- qcom,dpu-xtra-prefill-lines = <5>;
- qcom,dpu-dest-scale-prefill-lines = <6>;
- qcom,dpu-macrotile-prefill-lines = <7>;
- qcom,dpu-yuv-nv12-prefill-lines = <8>;
- qcom,dpu-linear-prefill-lines = <9>;
- qcom,dpu-downscaling-prefill-lines = <10>;
- qcom,dpu-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000
- 2400000 2400000 2400000 2400000>;
- qcom,dpu-amortizable-threshold = <11>;
-
- qcom,dpu-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
- qcom,dpu-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
-
- qcom,dpu-sspp-vig-blocks {
- qcom,dpu-vig-csc-off = <0x320>;
- qcom,dpu-vig-qseed-off = <0x200>;
- qcom,dpu-vig-qseed-size = <0x74>;
- /* Offset from vig top, version of HSIC */
- qcom,dpu-vig-hsic = <0x200 0x00010000>;
- qcom,dpu-vig-memcolor = <0x200 0x00010000>;
- qcom,dpu-vig-pcc = <0x1780 0x00010000>;
- };
-
- qcom,dpu-sspp-rgb-blocks {
- qcom,dpu-rgb-scaler-off = <0x200>;
- qcom,dpu-rgb-scaler-size = <0x74>;
- qcom,dpu-rgb-pcc = <0x380 0x00010000>;
- };
-
- qcom,dpu-dspp-blocks {
- qcom,dpu-dspp-igc = <0x0 0x00010000>;
- qcom,dpu-dspp-pcc = <0x1700 0x00010000>;
- qcom,dpu-dspp-gc = <0x17c0 0x00010000>;
- qcom,dpu-dspp-hsic = <0x0 0x00010000>;
- qcom,dpu-dspp-memcolor = <0x0 0x00010000>;
- qcom,dpu-dspp-sixzone = <0x0 0x00010000>;
- qcom,dpu-dspp-gamut = <0x1600 0x00010000>;
- qcom,dpu-dspp-dither = <0x0 0x00010000>;
- qcom,dpu-dspp-hist = <0x0 0x00010000>;
- qcom,dpu-dspp-vlut = <0x0 0x00010000>;
- };
-
- qcom,dpu-mixer-blocks {
- qcom,dpu-mixer-gc = <0x3c0 0x00010000>;
- };
-
qcom,msm-hdmi-audio-rx {
compatible = "qcom,msm-hdmi-audio-codec-rx";
};
- qcom,dpu-inline-rotator = <&mdss_rotator 0>;
- qcom,dpu-inline-rot-xin = <10 11>;
- qcom,dpu-inline-rot-xin-type = "sspp", "wb";
- qcom,dpu-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>;
-
qcom,platform-supply-entries {
#address-cells = <1>;
#size-cells = <0>;
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