> -----Original Message----- > From: Lucas Stach [mailto:l.stach@xxxxxxxxxxxxxx] > Sent: Friday, February 2, 2018 2:31 AM > To: Shawn Guo <shawnguo@xxxxxxxxxx> > Cc: Rob Herring <robh+dt@xxxxxxxxxx>; Mark Rutland > <mark.rutland@xxxxxxx>; Catalin Marinas <catalin.marinas@xxxxxxx>; Will > Deacon <will.deacon@xxxxxxx>; Fabio Estevam <fabio.estevam@xxxxxxx>; > dl-linux-imx <linux-imx@xxxxxxx>; devicetree@xxxxxxxxxxxxxxx; linux-arm- > kernel@xxxxxxxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx; patchwork- > lst@xxxxxxxxxxxxxx; A.s. Dong <aisheng.dong@xxxxxxx>; Baruch Siach > <baruch@xxxxxxxxxx> > Subject: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ > > This adds the basic DTS for the i.MX8MQ. > For now only the following peripherals are supported: > - IOMUXC (pin controller) > - CCM (clock controller) > - GPIO > - UART > - uSDHC (SD/eMMC controller) > - FEC (ethernet controller) > - i2c > > This is enough to get a very basic board support up and running. > > One known limitation is that the driver for the GPC interrupt > controller is still missing, rendering the CPU sleep states unusable > as there is nothing waking them up anymore. This will be fixed in > due course. > > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > --- > v2: > - move to freescale folder > - change compatibles to "fsl" vendor prefix > - remove unnecessary newlines > - move status property to be the last in all node > - remove imx21 compatibles from UART nodes > - document compatible > --- > Documentation/devicetree/bindings/arm/fsl.txt | 4 + > arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623 > +++++++++++++++++++++++++ Should this belongs to pinctrl part? > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 411 ++++++++++++++++ > 3 files changed, 1038 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h > create mode 100644 arch/arm64/boot/dts/freescale/imx8mq.dtsi > > diff --git a/Documentation/devicetree/bindings/arm/fsl.txt > b/Documentation/devicetree/bindings/arm/fsl.txt > index cdb9dd705754..85d1c9ec6fa3 100644 > --- a/Documentation/devicetree/bindings/arm/fsl.txt > +++ b/Documentation/devicetree/bindings/arm/fsl.txt > @@ -75,6 +75,10 @@ i.MX6q generic board > Required root node properties: > - compatible = "fsl,imx6q"; > > +i.MX8MQ generic board > +Required root node properties: > + - compatible = "fsl,imx8mq"; > + > Freescale Vybrid Platform Device Tree Bindings > ---------------------------------------------- > [...] > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > new file mode 100644 > index 000000000000..50ed302d299a > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -0,0 +1,411 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2017 NXP > + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@xxxxxxxxxxxxxx> > + */ > + > +#include <dt-bindings/clock/imx8mq-clock.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include "imx8mq-pinfunc.h" > + > +/* first 128 KiB of memory are owned by ATF */ > +/memreserve/ 0x40000000 0x00020000; > + > +/ { > + /* This should really be the GPC, but we need a driver for this first */ > + interrupt-parent = <&gic>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + i2c0 = &i2c1; > + i2c1 = &i2c2; > + i2c2 = &i2c3; > + i2c3 = &i2c4; > + serial0 = &uart1; > + serial1 = &uart2; > + serial2 = &uart3; > + serial3 = &uart4; > + }; > + > + ckil: clk-ckil { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + clock-output-names = "ckil"; > + }; > + > + osc_25m: clk-osc-25m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <25000000>; > + clock-output-names = "osc_25m"; > + }; > + > + osc_27m: clk-osc-27m { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <27000000>; > + clock-output-names = "osc_27m"; > + }; > + > + clk_ext1: clk-ext1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <133000000>; > + clock-output-names = "clk_ext1"; > + }; > + > + clk_ext2: clk-ext2 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <133000000>; > + clock-output-names = "clk_ext2"; > + }; > + > + clk_ext3: clk-ext3 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <133000000>; > + clock-output-names = "clk_ext3"; > + }; > + > + clk_ext4: clk-ext4 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency= <133000000>; > + clock-output-names = "clk_ext4"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + idle-states { > + entry-method = "psci"; > + > + CPU_SLEEP: cpu-sleep { > + compatible = "arm,idle-state"; > + arm,psci-suspend-param = <0x0010033>; > + local-timer-stop; > + entry-latency-us = <1000>; > + exit-latency-us = <700>; > + min-residency-us = <2700>; > + wakeup-latency-us = <1500>; > + }; > + }; > + > + A53_0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x0>; > + enable-method = "psci"; > + next-level-cache = <&A53_L2>; > + cpu-idle-states = <&CPU_SLEEP>; > + }; > + > + A53_1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x1>; > + enable-method = "psci"; > + next-level-cache = <&A53_L2>; > + cpu-idle-states = <&CPU_SLEEP>; > + }; > + > + A53_2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x2>; > + enable-method = "psci"; > + next-level-cache = <&A53_L2>; > + cpu-idle-states = <&CPU_SLEEP>; > + }; > + > + A53_3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x3>; > + enable-method = "psci"; > + next-level-cache = <&A53_L2>; > + cpu-idle-states = <&CPU_SLEEP>; > + }; > + > + A53_L2: l2-cache0 { > + compatible = "cache"; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | > IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | > IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | > IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | > IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ > + clock-frequency = <8333333>; Looks strange to me, why set that value? > + interrupt-parent = <&gic>; > + arm,no-tick-in-suspend; > + }; > + > + peripherals@0 { Any special purpose to create this? Regards Dong Aisheng > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x0 0x3e000000>; > + > + bus@30000000 { /* AIPS1 */ > + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x30000000 0x30000000 0x400000>; > + > + gpio1: gpio@30200000 { > + compatible = "fsl,imx8mq-gpio", "fsl,imx35- > gpio"; > + reg = <0x30200000 0x10000>; > + interrupts = <GIC_SPI 64 > IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio2: gpio@30210000 { > + compatible = "fsl,imx8mq-gpio", "fsl,imx35- > gpio"; > + reg = <0x30210000 0x10000>; > + interrupts = <GIC_SPI 66 > IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio3: gpio@30220000 { > + compatible = "fsl,imx8mq-gpio", "fsl,imx35- > gpio"; > + reg = <0x30220000 0x10000>; > + interrupts = <GIC_SPI 68 > IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio4: gpio@30230000 { > + compatible = "fsl,imx8mq-gpio", "fsl,imx35- > gpio"; > + reg = <0x30230000 0x10000>; > + interrupts = <GIC_SPI 70 > IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio5: gpio@30240000 { > + compatible = "fsl,imx8mq-gpio", "fsl,imx35- > gpio"; > + reg = <0x30240000 0x10000>; > + interrupts = <GIC_SPI 72 > IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + iomuxc: iomuxc@30330000 { > + compatible = "fsl,imx8mq-iomuxc"; > + reg = <0x30330000 0x10000>; > + }; > + > + gpr: iomuxc-gpr@30340000 { > + compatible = "fsl,imx8mq-iomuxc-gpr", > "syscon"; > + reg = <0x30340000 0x10000>; > + }; > + > + anatop: anatop@30360000 { > + compatible = "fsl,imx8mq-anatop", "syscon"; > + reg = <0x30360000 0x10000>; > + interrupts = <GIC_SPI 49 > IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + clk: clock-controller@30380000 { > + compatible = "fsl,imx8mq-ccm"; > + reg = <0x30380000 0x10000>; > + interrupts = <GIC_SPI 85 > IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; > + #clock-cells = <1>; > + clocks = <&ckil>, <&osc_25m>, <&osc_27m>, > + <&clk_ext1>, <&clk_ext2>, > + <&clk_ext3>, <&clk_ext4>; > + clock-names = "ckil", "osc_25m", "osc_27m", > + "clk_ext1", "clk_ext2", > + "clk_ext3", "clk_ext4"; > + }; > + }; > + > + bus@30400000 { /* AIPS2 */ > + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x30400000 0x30400000 0x400000>; > + }; > + > + bus@30800000 { /* AIPS3 */ > + compatible = "fsl,imx8mq-aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x30800000 0x30800000 0x400000>; > + > + uart1: serial@30860000 { > + compatible = "fsl,imx8mq-uart", > + "fsl,imx6q-uart"; > + reg = <0x30860000 0x10000>; > + interrupts = <GIC_SPI 26 > IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, > + <&clk IMX8MQ_CLK_UART1_ROOT>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart3: serial@30880000 { > + compatible = "fsl,imx8mq-uart", > + "fsl,imx6q-uart"; > + reg = <0x30880000 0x10000>; > + interrupts = <GIC_SPI 28 > IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, > + <&clk IMX8MQ_CLK_UART3_ROOT>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart2: serial@30890000 { > + compatible = "fsl,imx8mq-uart", > + "fsl,imx6q-uart"; > + reg = <0x30890000 0x10000>; > + interrupts = <GIC_SPI 27 > IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, > + <&clk IMX8MQ_CLK_UART2_ROOT>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + i2c1: i2c@30a20000 { > + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; > + reg = <0x30a20000 0x10000>; > + interrupts = <GIC_SPI 35 > IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c2: i2c@30a30000 { > + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; > + reg = <0x30a30000 0x10000>; > + interrupts = <GIC_SPI 36 > IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c3: i2c@30a40000 { > + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; > + reg = <0x30a40000 0x10000>; > + interrupts = <GIC_SPI 37 > IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c4: i2c@30a50000 { > + compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; > + reg = <0x30a50000 0x10000>; > + interrupts = <GIC_SPI 38 > IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + uart4: serial@30a60000 { > + compatible = "fsl,imx8mq-uart", > + "fsl,imx6q-uart"; > + reg = <0x30a60000 0x10000>; > + interrupts = <GIC_SPI 29 > IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, > + <&clk IMX8MQ_CLK_UART4_ROOT>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + usdhc1: usdhc@30b40000 { > + compatible = "fsl,imx8mq-usdhc", > + "fsl,imx7d-usdhc"; > + reg = <0x30b40000 0x10000>; > + interrupts = <GIC_SPI 22 > IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_DUMMY>, > + <&clk > IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, > + <&clk IMX8MQ_CLK_USDHC1_ROOT>; > + clock-names = "ipg", "ahb", "per"; > + fsl,tuning-start-tap = <20>; > + fsl,tuning-step = <2>; > + bus-width = <4>; > + status = "disabled"; > + }; > + > + usdhc2: usdhc@30b50000 { > + compatible = "fsl,imx8mq-usdhc", > + "fsl,imx7d-usdhc"; > + reg = <0x30b50000 0x10000>; > + interrupts = <GIC_SPI 23 > IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_DUMMY>, > + <&clk > IMX8MQ_CLK_NAND_USDHC_BUS_DIV>, > + <&clk IMX8MQ_CLK_USDHC2_ROOT>; > + clock-names = "ipg", "ahb", "per"; > + fsl,tuning-start-tap = <20>; > + fsl,tuning-step = <2>; > + bus-width = <4>; > + status = "disabled"; > + }; > + > + fec1: ethernet@30be0000 { > + compatible = "fsl,imx8mq-fec", "fsl,imx6sx- > fec"; > + reg = <0x30be0000 0x10000>; > + interrupts = <GIC_SPI 118 > IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, > + <&clk IMX8MQ_CLK_ENET1_ROOT>, > + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>, > + <&clk IMX8MQ_CLK_ENET_REF_DIV>, > + <&clk > IMX8MQ_CLK_ENET_PHY_REF_DIV>; > + clock-names = "ipg", "ahb", "ptp", > + "enet_clk_ref", "enet_out"; > + fsl,num-tx-queues = <3>; > + fsl,num-rx-queues = <3>; > + status = "disabled"; > + }; > + }; > + > + gic: interrupt-controller@38800000 { > + compatible = "arm,gic-v3"; > + reg = <0x38800000 0x10000>, /* GIC Dist */ > + <0x38880000 0xc0000>; /* GICR (RD_base + > SGI_base) */ > + #interrupt-cells = <3>; > + interrupt-controller; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&gic>; > + }; > + }; > +}; > -- > 2.15.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
