The LPC Host Interface Controller is part of a BMC SoC that is used for
communication with the host.
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Joel Stanley <joel@xxxxxxxxx>
---
v2:
- Move the content to below the Host Node Children heading
- Add Rob's review tag
---
.../devicetree/bindings/mfd/aspeed-lpc.txt | 41 ++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
index 514d82ced95b..69aadee00d5f 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
@@ -109,9 +109,50 @@ lpc: lpc@1e789000 {
};
};
+BMC Node Children
+==================
+
+
Host Node Children
==================
+LPC Host Interface Controller
+-------------------
+
+The LPC Host Interface Controller manages functions exposed to the host such as
+LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
+management and bus snoop configuration.
+
+Required properties:
+
+- compatible: One of:
+ "aspeed,ast2400-lpc-ctrl";
+ "aspeed,ast2500-lpc-ctrl";
+
+- reg: contains offset/length values of the host interface controller
+ memory regions
+
+- clocks: contains a phandle to the syscon node describing the clocks.
+ There should then be one cell representing the clock to use
+
+- memory-region: A phandle to a reserved_memory region to be used for the LPC
+ to AHB mapping
+
+- flash: A phandle to the SPI flash controller containing the flash to
+ be exposed over the LPC to AHB mapping
+
+Example:
+
+lpc-host@80 {
+ lpc_ctrl: lpc-ctrl@0 {
+ compatible = "aspeed,ast2500-lpc-ctrl";
+ reg = <0x0 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
+ };
+};
+
LPC Host Controller
-------------------
--
2.15.1
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