On Mon, Feb 12, 2018 at 06:33:26PM +0000, Jean-Philippe Brucker wrote: > On ARM systems, some platform devices behind an IOMMU may support stall > and PASID features. Stall is the ability to recover from page faults and > PASID offers multiple process address spaces to the device. Together they > allow to do paging with a device. Let the firmware tell us when a device > supports stall and PASID. > > Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@xxxxxxx> > --- > Documentation/devicetree/bindings/iommu/iommu.txt | 24 +++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iommu/iommu.txt b/Documentation/devicetree/bindings/iommu/iommu.txt > index 5a8b4624defc..8066b3852110 100644 > --- a/Documentation/devicetree/bindings/iommu/iommu.txt > +++ b/Documentation/devicetree/bindings/iommu/iommu.txt > @@ -86,6 +86,30 @@ have a means to turn off translation. But it is invalid in such cases to > disable the IOMMU's device tree node in the first place because it would > prevent any driver from properly setting up the translations. > > +Optional properties: > +-------------------- > +- dma-can-stall: When present, the master can wait for a transaction to > + complete for an indefinite amount of time. Upon translation fault some > + IOMMUs, instead of aborting the translation immediately, may first > + notify the driver and keep the transaction in flight. This allows the OS > + to inspect the fault and, for example, make physical pages resident > + before updating the mappings and completing the transaction. Such IOMMU > + accepts a limited number of simultaneous stalled transactions before > + having to either put back-pressure on the master, or abort new faulting > + transactions. > + > + Firmware has to opt-in stalling, because most buses and masters don't > + support it. In particular it isn't compatible with PCI, where > + transactions have to complete before a time limit. More generally it > + won't work in systems and masters that haven't been designed for > + stalling. For example the OS, in order to handle a stalled transaction, > + may attempt to retrieve pages from secondary storage in a stalled > + domain, leading to a deadlock. > + > +- pasid-bits: Some masters support multiple address spaces for DMA, by > + tagging DMA transactions with an address space identifier. By default, > + this is 0, which means that the device only has one address space. So 3 would mean 8 address spaces? Maybe pasid-num-bits would be a bit clearer. Either way, Reviewed-by: Rob Herring <robh@xxxxxxxxxx> Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
