On Tue, Feb 11, 2014 at 09:29:59AM +0000, Mohit Kumar wrote: > From: Pratyush Anand <pratyush.anand@xxxxxx> > > ST miphy40lp can be used with PCIe, SATA and Super Speed USB > controllers. SPEAr13XX SoCs use this phy for PCIe and SATA. > > Signed-off-by: Pratyush Anand <pratyush.anand@xxxxxx> > Cc: Mohit Kumar <mohit.kumar@xxxxxx> > Cc: Arnd Bergmann <arnd@xxxxxxxx> > Cc: Viresh Kumar <viresh.linux@xxxxxxxxx> > Cc: Kishon Vijay Abraham I <kishon@xxxxxx> > Cc: spear-devel@xxxxxxxxxxx > Cc: devicetree@xxxxxxxxxxxxxxx > --- > .../devicetree/bindings/phy/st-miphy40lp.txt | 18 ++++++++++++++++++ > 1 files changed, 18 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt > > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt > new file mode 100644 > index 0000000..1c8d04c > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt > @@ -0,0 +1,18 @@ > +ST miphy40lp DT detail > +=================================== > + > +miphy40lp is a phy controller from ST Microelectronics which supports PCIe, > +SATA and Super Speed USB host and devices. It has been used in SPEAr13xx SOCs. > + > +Required properties: > +- compatible : should be "st,miphy40lp-phy" > + Other supported soc specific compatible: > + "st,spear1310-miphy" > + "st,spear1340-miphy" > +- reg : offset and length of the PHY register set. > +- misc: phandle for the syscon node to access misc registers This is very vague. What is this used for? > +- phy-id: Instance id of the phy. > +- #phy-cells : from the generic PHY bindings, must be 1. > + - 1st cell: phandle to the phy node. > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe > + and 2 for Super Speed USB. One cell or two? Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
