Hi Kieran,
Thank you for the patch.
On Tuesday, 13 February 2018 21:30:36 EET Kieran Bingham wrote:
> From: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx>
>
> The VSPD includes a CLUT on RPF2. Ensure that the register space is
> mapped correctly to support this.
>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@xxxxxxxxxxxxxxxx>
Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 1f32340af2d1..772991db8820
> 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -2607,7 +2607,7 @@
>
> vspd0: vsp@fea20000 {
> compatible = "renesas,vsp2";
> - reg = <0 0xfea20000 0 0x4000>;
> + reg = <0 0xfea20000 0 0x8000>;
> interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpg CPG_MOD 623>;
> power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
> @@ -2627,7 +2627,7 @@
>
> vspd1: vsp@fea28000 {
> compatible = "renesas,vsp2";
> - reg = <0 0xfea28000 0 0x4000>;
> + reg = <0 0xfea28000 0 0x8000>;
> interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpg CPG_MOD 622>;
> power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
> @@ -2647,7 +2647,7 @@
>
> vspd2: vsp@fea30000 {
> compatible = "renesas,vsp2";
> - reg = <0 0xfea30000 0 0x4000>;
> + reg = <0 0xfea30000 0 0x8000>;
> interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpg CPG_MOD 621>;
> power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
--
Regards,
Laurent Pinchart
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