On 02/06/2018 10:52 AM, sean.wang@xxxxxxxxxxxx wrote:
> From: Sean Wang <sean.wang@xxxxxxxxxxxx>
>
> All ethsys, pciesys and ssusbsys internally include reset controller, so
> explicitly add back these missing cell definitions to related bindings
> and examples.
>
> Signed-off-by: Sean Wang <sean.wang@xxxxxxxxxxxx>
> Cc: Rob Herring <robh@xxxxxxxxxx>
> Cc: Stephen Boyd <sboyd@xxxxxxxxxxxxxx>
> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
> ---
> Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 2 ++
> Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt | 2 ++
> Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt | 2 ++
> 3 files changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> index 7aa3fa1..8f5335b 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
> @@ -9,6 +9,7 @@ Required Properties:
> - "mediatek,mt2701-ethsys", "syscon"
> - "mediatek,mt7622-ethsys", "syscon"
> - #clock-cells: Must be 1
> +- #reset-cells: Must be 1
>
> The ethsys controller uses the common clk binding from
> Documentation/devicetree/bindings/clock/clock-bindings.txt
> @@ -20,4 +21,5 @@ ethsys: clock-controller@1b000000 {
> compatible = "mediatek,mt2701-ethsys", "syscon";
> reg = <0 0x1b000000 0 0x1000>;
> #clock-cells = <1>;
> + #reset-cells = <1>;
The example is already fixed upstream, but I forgot the binding description,
please rebase this patch.
And please don't forget to add all clock maintainers.
Regards,
Matthias
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