Hi Benoit,
On Mon, Jan 29, 2018 at 01:10:36PM -0600, Benoit Parrot wrote:
> > + reg = csi2rx->num_lanes << 8;
> > + for (i = 0; i < csi2rx->num_lanes; i++)
> > + reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csi2rx->lanes[i]);
> > +
> > + for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++)
> > + reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, i + 1);
>
> Not sure why the above init loop is needed, but at any rate it could
> cause lane number collision. As far as I can see the MIPI spec does
> not require data lane to be consecutive or starting at a specific
> physical lane number.
I should probably add a comment there, but the hardware needs the data
lanes to have a mapping even though they are not in use. This was
addressing this behaviour but...
> Based on that the following DT node could be a valid configuration
> csi2_cam0: endpoint {
> clock-lanes = <0>;
> data-lanes = <2 3>;
> ...
> };
I obviously overlooked a few corner cases :)
Since the lanes are not in use, I'm not sure we have to worry about
lanes collision. Simon, would it cause any trouble if we map to lanes
to the same physical lane?
Thanks!
maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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