On Wed, Jan 17, 2018 at 09:14:10PM +0100, Jernej Skrabec wrote: > Currently, if one of the factors isn't present, bit 0 gets always set to > 1. For example, A83T has NMP PLLs modelled as NKMP PLL without K. Since > K is not specified, it's offset, width and shift is 0. Driver assumes > that lowest value possible is 1, otherwise we would get division by 0. > That situation causes that bit 0 is always set, which may change wanted > clock rate. > > Fix that by masking every factor according to it's specified width. > Factors with width set to 0 won't have any influence to final register > value. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@xxxxxxxx> Acked-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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