On Mon, Jan 08, 2018 at 10:04:51AM +0800, Anson Huang wrote: > Add 696MHz operating point for i.MX6UL, only for those > parts with speed grading fuse set to 2b'10 supports > 696MHz operating point, so, speed grading check is also > added for i.MX6UL in this patch, the clock tree for each > operating point are as below: > > 696MHz: > pll1 696000000 > pll1_bypass 696000000 > pll1_sys 696000000 > pll1_sw 696000000 > arm 696000000 > 528MHz: > pll2 528000000 > pll2_bypass 528000000 > pll2_bus 528000000 > ca7_secondary_sel 528000000 > step 528000000 > pll1_sw 528000000 > arm 528000000 > 396MHz: > pll2_pfd2_396m 396000000 > ca7_secondary_sel 396000000 > step 396000000 > pll1_sw 396000000 > arm 396000000 > 198MHz: > pll2_pfd2_396m 396000000 > ca7_secondary_sel 396000000 > step 396000000 > pll1_sw 396000000 > arm 198000000 > > Signed-off-by: Anson Huang <Anson.Huang@xxxxxxx> > Reviewed-by: Fabio Estevam <fabio.estevam@xxxxxxx> For this series: Acked-by: Dong Aisheng <aisheng.dong@xxxxxxx> Regards Dong Aisheng -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
