Hi, Dne torek, 02. januar 2018 ob 09:14:37 CET je Icenowy Zheng napisal(a): > 在 2018年1月2日星期二 CST 下午4:11:04，Chen-Yu Tsai 写道： > > > On Sat, Dec 30, 2017 at 7:30 PM, Icenowy Zheng <icenowy@xxxxxxx> wrote: > > > The H3/H5 SoCs have a HDMI output and a TV Composite output. > > > > > > Add simplefb nodes for these outputs. > > > > > > Signed-off-by: Icenowy Zheng <icenowy@xxxxxxx> > > > --- > > > Changes in v4: > > > - Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the > > > > > > clocks that are needed to display framebuffer to the monitor. > > > > Looks good. I assume you've tested this? It does continue to work > > with the bus and DDC clocks disabled, right? > > Yes. This patchset is tested in Orange Pi PC and SoPine w/ Baseboard "Model > A". I think DDC clock is misnamed and according to DW HDMI binding should be named ISFR (clock for special function registers). I did few test tests when writing U-Boot driver and it has to be enabled all the time for driver to work correctly. I did few additional tests few days back - if only DDC clock is enabled and PLL video/HDMI clock disabled, DW HDMI registers are accessible. I guess DDC clock in your case is not needed because controller is already configured correctly. Best regards, Jernej -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
